1 /* the problem: we have 82801dbm support in fb1, and 82801er in fb2.
2 * fb1 code is what we want, fb2 structure is needed however.
3 * so we need to get fb1 code for 82801dbm into fb2 structure.
5 /* What I did: took the 80801er stuff from fb2, verify it against the
6 * db stuff in fb1, and made sure it was right.
13 extern void i82801dbm_enable(device_t dev);
16 000 = Non-combined. P0 is primary master. P1 is secondary master.
17 001 = Non-combined. P0 is secondary master. P1 is primary master.
18 100 = Combined. P0 is primary master. P1 is primary slave. IDE is secondary; Primary IDE channel
20 101 = Combined. P0 is primary slave. P1 is primary master. IDE is secondary.
21 110 = Combined. IDE is primary. P0 is secondary master. P1 is secondary slave; Secondary IDE
23 111 = Combined. IDE is primary. P0 is secondary slave. P1 is secondary master.
26 #define PCI_DMA_CFG 0x90
27 #define SERIRQ_CNTL 0x64
31 #define GEN_PMCON_3 0xa4
35 #define ACPI_CNTL 0x44
36 #define BIOS_CNTL 0x4E
37 #define GPIO_BASE 0x58
38 #define GPIO_CNTL 0x5C
39 #define PIRQA_ROUT 0x60
40 #define PIRQE_ROUT 0x68
49 #define SUB_BUS_NUM 0x1A
57 #define PCI_MAST_STS 0x82
59 #define RTC_FAILED (1 <<2)
62 #define SMBUS_IO_BASE 0x1000
64 #define SMBHSTSTAT 0x0
67 #define SMBXMITADD 0x4
68 #define SMBHSTDAT0 0x5
69 #define SMBHSTDAT1 0x6
71 #define SMBTRNSADD 0x9
72 #define SMBSLVDATA 0xa
73 #define SMLINK_PIN_CTL 0xe
74 #define SMBUS_PIN_CTL 0xf
76 /* Between 1-10 seconds, We should never timeout normally
77 * Longer than this is just painful when a timeout condition occurs.
79 #define SMBUS_TIMEOUT (100*1000)
81 #endif /* I82801DBM_H */