2 * (C) 2003 Linux Networx, SuSE Linux AG
3 * (C) 2004 Tyan Computer
4 * (c) 2005 Digital Design Corporation
6 #include <console/console.h>
7 #include <device/device.h>
8 #include <device/pci.h>
9 #include <device/pci_ids.h>
10 #include <device/pci_ops.h>
11 #include <pc80/mc146818rtc.h>
12 #include <pc80/isa-dma.h>
18 #ifndef MAINBOARD_POWER_ON_AFTER_POWER_FAIL
19 #define MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
22 #define MAINBOARD_POWER_OFF 0
23 #define MAINBOARD_POWER_ON 1
26 void i82801ca_enable_ioapic( struct device *dev)
29 volatile uint32_t* ioapic_index = (volatile uint32_t*)0xfec00000;
30 volatile uint32_t* ioapic_data = (volatile uint32_t*)0xfec00010;
32 dword = pci_read_config32(dev, GEN_CNTL);
33 dword |= (3 << 7); /* enable ioapic & disable SMBus interrupts */
34 dword |= (1 <<13); /* coprocessor error enable */
35 dword |= (1 << 1); /* delay transaction enable */
36 dword |= (1 << 2); /* DMA collection buf enable */
37 pci_write_config32(dev, GEN_CNTL, dword);
38 printk_debug("ioapic southbridge enabled %x\n",dword);
40 // Must program the APIC's ID before using it
42 *ioapic_index = 0; // Select APIC ID register
43 *ioapic_data = (2<<24);
45 // Hang if the ID didn't take (chip not present?)
48 printk_debug("Southbridge apic id = %x\n", (dword>>24) & 0xF);
52 *ioapic_index = 3; // Select Boot Configuration register
53 *ioapic_data = 1; // Use Processor System Bus to deliver interrupts
56 // This is how interrupts are received from the Super I/O chip
57 void i82801ca_enable_serial_irqs( struct device *dev)
59 // Recognize serial IRQs, continuous mode, frame size 21, 4 clock start frame pulse width
60 pci_write_config8(dev, SERIRQ_CNTL, (1 << 7)|(1 << 6)|((21 - 17) << 2)|(0<< 0));
63 //----------------------------------------------------------------------------------
64 // Function: i82801ca_lpc_route_dma
66 // mask - identifies whether each channel should be used for PCI DMA
67 // (bit = 0) or LPC DMA (bit = 1). The LSb controls channel 0.
68 // Channel 4 is not used (reserved).
70 // Description: Route all DMA channels to either PCI or LPC.
72 void i82801ca_lpc_route_dma( struct device *dev, uint8_t mask)
77 dmaConfig = pci_read_config16(dev, PCI_DMA_CFG);
78 dmaConfig &= 0x300; // Preserve reserved bits
79 for(channelIndex = 0; channelIndex < 8; channelIndex++) {
80 if (channelIndex == 4)
81 continue; // Register doesn't support channel 4
82 dmaConfig |= ((mask & (1 << channelIndex))? 3:1) << (channelIndex*2);
84 pci_write_config16(dev, PCI_DMA_CFG, dmaConfig);
87 void i82801ca_rtc_init(struct device *dev)
91 int pwr_on = MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
92 uint8_t pmcon3 = pci_read_config8(dev, GEN_PMCON_3);
94 rtc_failed = pmcon3 & RTC_BATTERY_DEAD;
96 // Clear the RTC_BATTERY_DEAD bit, but preserve
97 // the RTC_POWER_FAILED, G3 state, and reserved bits
98 // NOTE: RTC_BATTERY_DEAD and RTC_POWER_FAILED are "write-1-clear" bits
99 pmcon3 &= ~RTC_POWER_FAILED;
102 get_option(&pwr_on, "power_on_after_fail");
103 pmcon3 &= ~SLEEP_AFTER_POWER_FAIL;
105 pmcon3 |= SLEEP_AFTER_POWER_FAIL;
107 pci_write_config8(dev, GEN_PMCON_3, pmcon3);
108 printk_info("set power %s after power fail\n",
109 pwr_on ? "on" : "off");
111 // See if the Safe Mode jumper is set
112 dword = pci_read_config32(dev, GEN_STS);
113 rtc_failed |= dword & (1 << 2);
115 rtc_init(rtc_failed);
119 void i82801ca_1f0_misc(struct device *dev)
121 // Prevent LPC disabling, enable parity errors, and SERR# (System Error)
122 pci_write_config16(dev, PCI_COMMAND, 0x014f);
124 // Set ACPI base address to 0x1100 (I/O space)
125 pci_write_config32(dev, PMBASE, 0x00001101);
127 // Enable ACPI I/O and power management
128 pci_write_config8(dev, ACPI_CNTL, 0x10);
130 // Set GPIO base address to 0x1180 (I/O space)
131 pci_write_config32(dev, GPIO_BASE, 0x00001181);
134 pci_write_config8(dev, GPIO_CNTL, 0x10);
136 // Route PIRQA to IRQ11, PIRQB to IRQ3, PIRQC to IRQ5, PIRQD to IRQ10
137 pci_write_config32(dev, PIRQA_ROUT, 0x0A05030B);
139 // Route PIRQE to IRQ7. Leave PIRQF - PIRQH unrouted.
140 pci_write_config8(dev, PIRQE_ROUT, 0x07);
142 // Enable access to the upper 128 byte bank of CMOS RAM
143 pci_write_config8(dev, RTC_CONF, 0x04);
145 // Decode 0x3F8-0x3FF (COM1) for COMA port,
146 // 0x2F8-0x2FF (COM2) for COMB
147 pci_write_config8(dev, COM_DEC, 0x10);
149 // LPT decode defaults to 0x378-0x37F and 0x778-0x77F
150 // Floppy decode defaults to 0x3F0-0x3F5, 0x3F7
152 // Enable COMA, COMB, LPT, floppy;
153 // disable microcontroller, Super I/O, sound, gameport
154 pci_write_config16(dev, LPC_EN, 0x000F);
157 static void lpc_init(struct device *dev)
163 /* IO APIC initialization */
164 i82801ca_enable_ioapic(dev);
166 i82801ca_enable_serial_irqs(dev);
168 /* power after power fail */
169 /* FIXME this doesn't work! */
170 /* Which state do we want to goto after g3 (power restored)?
174 byte = pci_read_config8(dev, GEN_PMCON_3);
176 byte &= ~1; // Return to S0 (boot) after power is re-applied
178 byte |= 1; // Return to S5
179 pci_write_config8(dev, GEN_PMCON_3, byte);
180 printk_info("set power %s after power fail\n", pwr_on?"on":"off");
182 /* Set up NMI on errors */
184 byte &= ~(1 << 3); /* IOCHK# NMI Enable */
185 byte &= ~(1 << 2); /* PCI SERR# Enable */
188 nmi_option = NMI_OFF;
189 get_option(&nmi_option, "nmi");
191 byte &= ~(1 << 7); /* set NMI */
195 /* Initialize the real time clock */
196 i82801ca_rtc_init(dev);
198 i82801ca_lpc_route_dma(dev, 0xff);
200 /* Initialize isa dma */
203 i82801ca_1f0_misc(dev);
206 static void i82801ca_lpc_read_resources(device_t dev)
208 struct resource *res;
210 /* Get the normal pci resources of this device */
211 pci_dev_read_resources(dev);
213 /* Add an extra subtractive resource for both memory and I/O */
214 res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
215 res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
217 res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
218 res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
221 static void i82801ca_lpc_enable_resources(device_t dev)
223 pci_dev_enable_resources(dev);
224 enable_childrens_resources(dev);
227 static struct device_operations lpc_ops = {
228 .read_resources = i82801ca_lpc_read_resources,
229 .set_resources = pci_dev_set_resources,
230 .enable_resources = i82801ca_lpc_enable_resources,
232 .scan_bus = scan_static_bus,
236 static const struct pci_driver lpc_driver __pci_driver = {
238 .vendor = PCI_VENDOR_ID_INTEL,
239 .device = PCI_DEVICE_ID_INTEL_82801CA_LPC,