6 extern void i82801ca_enable(device_t dev);
\r
10 #define PCI_DMA_CFG 0x90
11 #define SERIRQ_CNTL 0x64
15 #define GEN_PMCON_3 0xa4
18 #define ACPI_CNTL 0x44
19 #define BIOS_CNTL 0x4E
20 #define GPIO_BASE 0x58
21 #define GPIO_CNTL 0x5C
22 #define PIRQA_ROUT 0x60
23 #define PIRQE_ROUT 0x68
29 #define RTC_BATTERY_DEAD (1<<2)
\r
30 #define RTC_POWER_FAILED (1<<1)
\r
31 #define SLEEP_AFTER_POWER_FAIL (1<<0)
33 /********************************************************************/
\r
34 /* IDE Controller */
\r
35 /********************************************************************/
\r
37 // PCI Configuration Space (D31:F1)
\r
38 #define IDE_TIM_PRI 0x40 // IDE timings, primary
\r
39 #define IDE_TIM_SEC 0x42 // IDE timings, secondary
\r
43 #define IDE_DECODE_ENABLE (1<<15)
\r
45 /********************************************************************/
\r
47 /********************************************************************/
\r
49 // PCI Configuration Space (D31:F3)
\r
54 #define I2C_EN (1<<2)
\r
55 #define SMB_SMI_EN (1<<1)
\r
56 #define HST_EN (1<<0)
\r
58 #define SMBUS_IO_BASE 0x1000
60 // I/O registers (relative to SMBUS_IO_BASE)
70 #define SMLINK_PIN_CTL 14
71 #define SMBUS_PIN_CTL 15
73 /* Between 1-10 seconds, We should never timeout normally
74 * Longer than this is just painful when a timeout condition occurs.
76 #define SMBUS_TIMEOUT (100*1000)
78 #endif /* I82801CA_H */