2 * This file is part of the coreboot project.
4 * Copyright (C) 2003 Linux Networx
5 * Copyright (C) 2003 SuSE Linux AG
6 * Copyright (C) 2005 Tyan Computer
7 * (Written by Yinghai Lu <yinghailu@gmail.com> for Tyan Computer)
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
24 #include <console/console.h>
25 #include <device/device.h>
26 #include <device/pci.h>
27 #include <device/pci_ids.h>
28 #include <pc80/mc146818rtc.h>
29 #include <pc80/isa-dma.h>
31 #include <arch/ioapic.h>
36 typedef struct southbridge_intel_i82801bx_config config_t;
38 /* PIRQ[n]_ROUT[3:0] - PIRQ Routing Control
39 * 0x00 - 0000 = Reserved
40 * 0x01 - 0001 = Reserved
41 * 0x02 - 0010 = Reserved
47 * 0x08 - 1000 = Reserved
52 * 0x0D - 1101 = Reserved
56 * PIRQ[n]_ROUT[7] - Interrupt Routing Enable (IRQEN)
57 * 0 - The PIRQ is routed to the ISA-compatible interrupt specified above.
58 * 1 - The PIRQ is not routed to the 8259.
71 * Use 0x0ef8 for a bitmap to cover all these IRQ's.
72 * Use the defined IRQ values above or set mainboard
73 * specific IRQ values in your devicetree.cb.
75 static void i82801bx_enable_apic(struct device *dev)
78 volatile uint32_t *ioapic_index = (volatile uint32_t *)IO_APIC_ADDR;
79 volatile uint32_t *ioapic_data = (volatile uint32_t *)(IO_APIC_ADDR + 0x10);
81 /* Set ACPI base address (I/O space). */
82 pci_write_config32(dev, PMBASE, (PMBASE_ADDR | 1));
84 /* Enable ACPI I/O range decode and ACPI power management. */
85 pci_write_config8(dev, ACPI_CNTL, ACPI_EN);
87 reg32 = pci_read_config32(dev, GEN_CNTL);
88 reg32 |= (1 << 13); /* Coprocessor error enable (COPR_ERR_EN) */
89 reg32 |= (3 << 7); /* IOAPIC enable (APIC_EN) */
90 reg32 |= (1 << 2); /* DMA collection buffer enable (DCB_EN) */
91 reg32 |= (1 << 1); /* Delayed transaction enable (DTE) */
92 pci_write_config32(dev, GEN_CNTL, reg32);
93 printk(BIOS_DEBUG, "IOAPIC Southbridge enabled %x\n", reg32);
96 *ioapic_data = (1 << 25);
100 printk(BIOS_DEBUG, "Southbridge APIC ID = %x\n", reg32);
101 if (reg32 != (1 << 25))
104 /* TODO: From i82801ca, needed/useful on other ICH? */
105 *ioapic_index = 3; /* Select Boot Configuration register. */
106 *ioapic_data = 1; /* Use Processor System Bus to deliver interrupts. */
109 static void i82801bx_enable_serial_irqs(struct device *dev)
111 /* Set packet length and toggle silent mode bit. */
112 pci_write_config8(dev, SERIRQ_CNTL,
113 (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0));
114 pci_write_config8(dev, SERIRQ_CNTL,
115 (1 << 7) | (0 << 6) | ((21 - 17) << 2) | (0 << 0));
116 /* TODO: Explain/#define the real meaning of these magic numbers. */
119 static void i82801bx_pirq_init(device_t dev, uint16_t ich_model)
122 config_t *config = dev->chip_info;
124 reg8 = (config->pirqa_routing) ? config->pirqa_routing : PIRQA;
125 pci_write_config8(dev, PIRQA_ROUT, reg8);
127 reg8 = (config->pirqb_routing) ? config->pirqb_routing : PIRQB;
128 pci_write_config8(dev, PIRQB_ROUT, reg8);
130 reg8 = (config->pirqc_routing) ? config->pirqc_routing : PIRQC;
131 pci_write_config8(dev, PIRQC_ROUT, reg8);
133 reg8 = (config->pirqd_routing) ? config->pirqd_routing : PIRQD;
134 pci_write_config8(dev, PIRQD_ROUT, reg8);
137 reg8 = (config->pirqe_routing) ? config->pirqe_routing : PIRQE;
138 pci_write_config8(dev, PIRQE_ROUT, reg8);
140 reg8 = (config->pirqf_routing) ? config->pirqf_routing : PIRQF;
141 pci_write_config8(dev, PIRQF_ROUT, reg8);
143 reg8 = (config->pirqg_routing) ? config->pirqg_routing : PIRQG;
144 pci_write_config8(dev, PIRQG_ROUT, reg8);
146 reg8 = (config->pirqh_routing) ? config->pirqh_routing : PIRQH;
147 pci_write_config8(dev, PIRQH_ROUT, reg8);
150 static void i82801bx_power_options(device_t dev)
156 /* power after power fail */
157 /* FIXME this doesn't work! */
158 /* Which state do we want to goto after g3 (power restored)?
162 pci_write_config8(dev, GEN_PMCON_3, pwr_on ? 0 : 1);
163 printk(BIOS_INFO, "Set power %s if power fails\n", pwr_on ? "on" : "off");
165 /* Set up NMI on errors. */
167 byte &= ~(1 << 3); /* IOCHK# NMI Enable */
168 byte &= ~(1 << 2); /* PCI SERR# Enable */
172 nmi_option = NMI_OFF;
173 get_option(&nmi_option, "nmi");
175 byte &= ~(1 << 7); /* Set NMI. */
180 static void gpio_init(device_t dev)
182 /* Set the value for GPIO base address register and enable GPIO. */
183 pci_write_config32(dev, GPIO_BASE, (GPIO_BASE_ADDR | 1));
184 pci_write_config8(dev, GPIO_CNTL, GPIO_EN);
187 static void i82801bx_rtc_init(struct device *dev)
193 reg8 = pci_read_config8(dev, GEN_PMCON_3);
194 rtc_failed = reg8 & RTC_BATTERY_DEAD;
196 reg8 &= ~(1 << 1); /* Preserve the power fail state. */
197 pci_write_config8(dev, GEN_PMCON_3, reg8);
199 reg32 = pci_read_config32(dev, GEN_STS);
200 rtc_failed |= reg32 & (1 << 2);
201 rtc_init(rtc_failed);
203 /* Enable access to the upper 128 byte bank of CMOS RAM. */
204 pci_write_config8(dev, RTC_CONF, 0x04);
207 static void i82801bx_lpc_route_dma(struct device *dev, uint8_t mask)
212 reg16 = pci_read_config16(dev, PCI_DMA_CFG);
214 for (i = 0; i < 8; i++) {
217 reg16 |= ((mask & (1 << i)) ? 3 : 1) << (i * 2);
219 pci_write_config16(dev, PCI_DMA_CFG, reg16);
222 static void i82801bx_lpc_decode_en(device_t dev, uint16_t ich_model)
224 /* Decode 0x3F8-0x3FF (COM1) for COMA port, 0x2F8-0x2FF (COM2) for COMB.
225 * LPT decode defaults to 0x378-0x37F and 0x778-0x77F.
226 * Floppy decode defaults to 0x3F0-0x3F5, 0x3F7.
227 * We also need to set the value for LPC I/F Enables Register.
229 pci_write_config8(dev, COM_DEC, 0x10);
230 pci_write_config16(dev, LPC_EN, 0x300F);
233 static void lpc_init(struct device *dev)
235 uint16_t ich_model = pci_read_config16(dev, PCI_DEVICE_ID);
237 /* Set the value for PCI command register. */
238 pci_write_config16(dev, PCI_COMMAND, 0x000f);
240 /* IO APIC initialization. */
241 i82801bx_enable_apic(dev);
243 i82801bx_enable_serial_irqs(dev);
245 /* Setup the PIRQ. */
246 i82801bx_pirq_init(dev, ich_model);
248 /* Setup power options. */
249 i82801bx_power_options(dev);
251 /* Set the state of the GPIO lines. */
254 /* Initialize the real time clock. */
255 i82801bx_rtc_init(dev);
258 i82801bx_lpc_route_dma(dev, 0xff);
260 /* Initialize ISA DMA. */
263 /* Setup decode ports and LPC I/F enables. */
264 i82801bx_lpc_decode_en(dev, ich_model);
267 static void i82801bx_lpc_read_resources(device_t dev)
269 struct resource *res;
271 /* Get the normal PCI resources of this device. */
272 pci_dev_read_resources(dev);
274 /* Add an extra subtractive resource for both memory and I/O. */
275 res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
278 res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
279 IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
281 res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
282 res->base = 0xff800000;
283 res->size = 0x00800000; /* 8 MB for flash */
284 res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
285 IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
287 res = new_resource(dev, 3); /* IOAPIC */
288 res->base = IO_APIC_ADDR;
289 res->size = 0x00001000;
290 res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
293 static struct device_operations lpc_ops = {
294 .read_resources = i82801bx_lpc_read_resources,
295 .set_resources = pci_dev_set_resources,
296 .enable_resources = pci_dev_enable_resources,
298 .scan_bus = scan_static_bus,
299 .enable = i82801bx_enable,
302 /* 82801BA/BAM (ICH2/ICH2-M) */
303 static const struct pci_driver i82801ba_lpc __pci_driver = {
305 .vendor = PCI_VENDOR_ID_INTEL,