2 * This file is part of the coreboot project.
4 * Copyright (C) 2003 Linux Networx
5 * Copyright (C) 2003 SuSE Linux AG
6 * Copyright (C) 2005 Tyan Computer
7 * (Written by Yinghai Lu <yinghailu@gmail.com> for Tyan Computer)
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
24 /* From 82801DBM, needs to be fixed to support everything the 82801ER does. */
26 #include <console/console.h>
27 #include <device/device.h>
28 #include <device/pci.h>
29 #include <device/pci_ids.h>
30 #include <pc80/mc146818rtc.h>
31 #include <pc80/isa-dma.h>
35 #define GPIO_BASE_ADDR 0x00000500 /* GPIO Base Address Register */
39 typedef struct southbridge_intel_i82801bx_config config_t;
41 /* PIRQ[n]_ROUT[3:0] - PIRQ Routing Control
42 * 0x00 - 0000 = Reserved
43 * 0x01 - 0001 = Reserved
44 * 0x02 - 0010 = Reserved
50 * 0x08 - 1000 = Reserved
55 * 0x0D - 1101 = Reserved
58 * PIRQ[n]_ROUT[7] - PIRQ Routing Control
59 * 0x80 - The PIRQ is not routed.
72 * Use 0x0ef8 for a bitmap to cover all these IRQ's.
73 * Use the defined IRQ values above or set mainboard
74 * specific IRQ values in your mainboards Config.lb.
77 void i82801bx_enable_apic(struct device *dev)
80 volatile uint32_t *ioapic_index = (volatile uint32_t *)0xfec00000;
81 volatile uint32_t *ioapic_data = (volatile uint32_t *)0xfec00010;
83 /* Set ACPI base address (I/O space). */
84 pci_write_config32(dev, PMBASE, (PMBASE_ADDR | 1));
86 /* Enable ACPI I/O and power management. */
87 pci_write_config8(dev, ACPI_CNTL, 0x10);
89 reg32 = pci_read_config32(dev, GEN_CNTL);
90 reg32 |= (3 << 7); /* Enable IOAPIC */
91 reg32 |= (1 << 13); /* Coprocessor error enable */
92 reg32 |= (1 << 1); /* Delayed transaction enable */
93 reg32 |= (1 << 2); /* DMA collection buffer enable */
94 pci_write_config32(dev, GEN_CNTL, reg32);
95 printk(BIOS_DEBUG, "IOAPIC Southbridge enabled %x\n", reg32);
98 *ioapic_data = (1 << 25);
101 reg32 = *ioapic_data;
102 printk(BIOS_DEBUG, "Southbridge APIC ID = %x\n", reg32);
103 if (reg32 != (1 << 25))
106 /* TODO: From i82801ca, needed/useful on other ICH? */
107 *ioapic_index = 3; /* Select Boot Configuration register. */
108 *ioapic_data = 1; /* Use Processor System Bus to deliver interrupts. */
111 void i82801bx_enable_serial_irqs(struct device *dev)
113 /* Set packet length and toggle silent mode bit. */
114 pci_write_config8(dev, SERIRQ_CNTL,
115 (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0));
116 pci_write_config8(dev, SERIRQ_CNTL,
117 (1 << 7) | (0 << 6) | ((21 - 17) << 2) | (0 << 0));
118 /* TODO: Explain/#define the real meaning of these magic numbers. */
121 static void i82801bx_pirq_init(device_t dev, uint16_t ich_model)
123 /* Get the chip configuration */
124 config_t *config = dev->chip_info;
126 if (config->pirqa_routing) {
127 pci_write_config8(dev, PIRQA_ROUT, config->pirqa_routing);
129 pci_write_config8(dev, PIRQA_ROUT, PIRQA);
132 if (config->pirqb_routing) {
133 pci_write_config8(dev, PIRQB_ROUT, config->pirqb_routing);
135 pci_write_config8(dev, PIRQB_ROUT, PIRQB);
138 if (config->pirqc_routing) {
139 pci_write_config8(dev, PIRQC_ROUT, config->pirqc_routing);
141 pci_write_config8(dev, PIRQC_ROUT, PIRQC);
144 if (config->pirqd_routing) {
145 pci_write_config8(dev, PIRQD_ROUT, config->pirqd_routing);
147 pci_write_config8(dev, PIRQD_ROUT, PIRQD);
150 /* Route PIRQE - PIRQH (for ICH2-ICH9). */
151 if (ich_model >= 0x2440) {
153 if (config->pirqe_routing) {
154 pci_write_config8(dev, PIRQE_ROUT, config->pirqe_routing);
156 pci_write_config8(dev, PIRQE_ROUT, PIRQE);
159 if (config->pirqf_routing) {
160 pci_write_config8(dev, PIRQF_ROUT, config->pirqf_routing);
162 pci_write_config8(dev, PIRQF_ROUT, PIRQF);
165 if (config->pirqg_routing) {
166 pci_write_config8(dev, PIRQG_ROUT, config->pirqg_routing);
168 pci_write_config8(dev, PIRQG_ROUT, PIRQG);
171 if (config->pirqh_routing) {
172 pci_write_config8(dev, PIRQH_ROUT, config->pirqh_routing);
174 pci_write_config8(dev, PIRQH_ROUT, PIRQH);
179 static void i82801bx_power_options(device_t dev)
185 /* power after power fail */
186 /* FIXME this doesn't work! */
187 /* Which state do we want to goto after g3 (power restored)?
191 pci_write_config8(dev, GEN_PMCON_3, pwr_on ? 0 : 1);
192 printk(BIOS_INFO, "Set power %s if power fails\n", pwr_on ? "on" : "off");
194 /* Set up NMI on errors. */
196 byte &= ~(1 << 3); /* IOCHK# NMI Enable */
197 byte &= ~(1 << 2); /* PCI SERR# Enable */
201 nmi_option = NMI_OFF;
202 get_option(&nmi_option, "nmi");
204 byte &= ~(1 << 7); /* Set NMI. */
209 static void gpio_init(device_t dev, uint16_t ich_model)
211 /* Set the value for GPIO base address register and enable GPIO.
212 * Note: ICH-ICH5 registers differ from ICH6-ICH9.
214 if (ich_model <= 0x24D0) {
215 pci_write_config32(dev, GPIO_BASE_ICH0_5, (GPIO_BASE_ADDR | 1));
216 pci_write_config8(dev, GPIO_CNTL_ICH0_5, 0x10);
217 } else if (ich_model >= 0x2640) {
218 pci_write_config32(dev, GPIO_BASE_ICH6_9, (GPIO_BASE_ADDR | 1));
219 pci_write_config8(dev, GPIO_CNTL_ICH6_9, 0x10);
223 void i82801bx_rtc_init(struct device *dev)
229 reg8 = pci_read_config8(dev, GEN_PMCON_3);
230 rtc_failed = reg8 & RTC_BATTERY_DEAD;
232 reg8 &= ~(1 << 1); /* Preserve the power fail state. */
233 pci_write_config8(dev, GEN_PMCON_3, reg8);
235 reg32 = pci_read_config32(dev, GEN_STS);
236 rtc_failed |= reg32 & (1 << 2);
237 rtc_init(rtc_failed);
239 /* Enable access to the upper 128 byte bank of CMOS RAM. */
240 pci_write_config8(dev, RTC_CONF, 0x04);
243 void i82801bx_lpc_route_dma(struct device *dev, uint8_t mask)
248 reg16 = pci_read_config16(dev, PCI_DMA_CFG);
250 for (i = 0; i < 8; i++) {
253 reg16 |= ((mask & (1 << i)) ? 3 : 1) << (i * 2);
255 pci_write_config16(dev, PCI_DMA_CFG, reg16);
258 static void i82801bx_lpc_decode_en(device_t dev, uint16_t ich_model)
260 /* Decode 0x3F8-0x3FF (COM1) for COMA port, 0x2F8-0x2FF (COM2) for COMB.
261 * LPT decode defaults to 0x378-0x37F and 0x778-0x77F.
262 * Floppy decode defaults to 0x3F0-0x3F5, 0x3F7.
263 * We also need to set the value for LPC I/F Enables Register.
264 * Note: ICH-ICH5 registers differ from ICH6-ICH9.
266 if (ich_model <= 0x24D0) {
267 pci_write_config8(dev, COM_DEC, 0x10);
268 pci_write_config16(dev, LPC_EN_ICH0_5, 0x300F);
269 } else if (ich_model >= 0x2640) {
270 pci_write_config8(dev, LPC_IO_DEC, 0x10);
271 pci_write_config16(dev, LPC_EN_ICH6_9, 0x300F);
275 static void lpc_init(struct device *dev)
277 uint16_t ich_model = pci_read_config16(dev, PCI_DEVICE_ID);
279 /* Set the value for PCI command register. */
280 pci_write_config16(dev, PCI_COMMAND, 0x000f);
282 /* IO APIC initialization. */
283 i82801bx_enable_apic(dev);
285 i82801bx_enable_serial_irqs(dev);
287 /* Setup the PIRQ. */
288 i82801bx_pirq_init(dev, ich_model);
290 /* Setup power options. */
291 i82801bx_power_options(dev);
293 /* Set the state of the GPIO lines. */
294 gpio_init(dev, ich_model);
296 /* Initialize the real time clock. */
297 i82801bx_rtc_init(dev);
300 i82801bx_lpc_route_dma(dev, 0xff);
302 /* Initialize ISA DMA. */
305 /* Setup decode ports and LPC I/F enables. */
306 i82801bx_lpc_decode_en(dev, ich_model);
309 static void i82801bx_lpc_read_resources(device_t dev)
311 struct resource *res;
313 /* Get the normal PCI resources of this device. */
314 pci_dev_read_resources(dev);
316 /* Add an extra subtractive resource for both memory and I/O. */
317 res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
320 res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
321 IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
323 res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
324 res->base = 0xff800000;
325 res->size = 0x00800000; /* 8 MB for flash */
326 res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
327 IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
329 res = new_resource(dev, 3); /* IOAPIC */
330 res->base = 0xfec00000;
331 res->size = 0x00001000;
332 res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
335 static void i82801bx_lpc_enable_resources(device_t dev)
337 pci_dev_enable_resources(dev);
338 enable_childrens_resources(dev);
341 static struct device_operations lpc_ops = {
342 .read_resources = i82801bx_lpc_read_resources,
343 .set_resources = pci_dev_set_resources,
344 .enable_resources = i82801bx_lpc_enable_resources,
346 .scan_bus = scan_static_bus,
347 .enable = i82801bx_enable,
350 static const struct pci_driver i82801aa_lpc __pci_driver = {
352 .vendor = PCI_VENDOR_ID_INTEL,
356 static const struct pci_driver i82801ab_lpc __pci_driver = {
358 .vendor = PCI_VENDOR_ID_INTEL,
362 static const struct pci_driver i82801ba_lpc __pci_driver = {
364 .vendor = PCI_VENDOR_ID_INTEL,
368 static const struct pci_driver i82801ca_lpc __pci_driver = {
370 .vendor = PCI_VENDOR_ID_INTEL,
374 static const struct pci_driver i82801db_lpc __pci_driver = {
376 .vendor = PCI_VENDOR_ID_INTEL,
380 static const struct pci_driver i82801dbm_lpc __pci_driver = {
382 .vendor = PCI_VENDOR_ID_INTEL,
386 /* 82801EB and 82801ER */
387 static const struct pci_driver i82801ex_lpc __pci_driver = {
389 .vendor = PCI_VENDOR_ID_INTEL,