src/southbridge/intel/i82801ax/i82801ax_lpc.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2003 Linux Networx
   5  * Copyright (C) 2003 SuSE Linux AG
   6  * Copyright (C) 2005 Tyan Computer
   7  * (Written by Yinghai Lu <yinghailu@gmail.com> for Tyan Computer)
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; either version 2 of the License, or
  12  * (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  22  */
  23
  24 /* From 82801DBM, needs to be fixed to support everything the 82801ER does. */
  25
  26 #include <console/console.h>
  27 #include <device/device.h>
  28 #include <device/pci.h>
  29 #include <device/pci_ids.h>
  30 #include <pc80/mc146818rtc.h>
  31 #include <pc80/isa-dma.h>
  32 #include <arch/io.h>
  33 #include "i82801ax.h"
  34
  35 #define GPIO_BASE_ADDR  0x00000500 /* GPIO Base Address Register */
  36
  37 #define NMI_OFF 0
  38
  39 typedef struct southbridge_intel_i82801ax_config config_t;
  40
  41 /* PIRQ[n]_ROUT[3:0] - PIRQ Routing Control
  42  * 0x00 - 0000 = Reserved
  43  * 0x01 - 0001 = Reserved
  44  * 0x02 - 0010 = Reserved
  45  * 0x03 - 0011 = IRQ3
  46  * 0x04 - 0100 = IRQ4
  47  * 0x05 - 0101 = IRQ5
  48  * 0x06 - 0110 = IRQ6
  49  * 0x07 - 0111 = IRQ7
  50  * 0x08 - 1000 = Reserved
  51  * 0x09 - 1001 = IRQ9
  52  * 0x0A - 1010 = IRQ10
  53  * 0x0B - 1011 = IRQ11
  54  * 0x0C - 1100 = IRQ12
  55  * 0x0D - 1101 = Reserved
  56  * 0x0E - 1110 = IRQ14
  57  * 0x0F - 1111 = IRQ15
  58  * PIRQ[n]_ROUT[7] - PIRQ Routing Control
  59  * 0x80 - The PIRQ is not routed.
  60  */
  61
  62 #define PIRQA 0x03
  63 #define PIRQB 0x04
  64 #define PIRQC 0x05
  65 #define PIRQD 0x06
  66 #define PIRQE 0x07
  67 #define PIRQF 0x09
  68 #define PIRQG 0x0A
  69 #define PIRQH 0x0B
  70
  71 /*
  72  * Use 0x0ef8 for a bitmap to cover all these IRQ's.
  73  * Use the defined IRQ values above or set mainboard
  74  * specific IRQ values in your mainboards Config.lb.
  75 */
  76
  77 void i82801ax_enable_apic(struct device *dev)
  78 {
  79         uint32_t reg32;
  80         volatile uint32_t *ioapic_index = (volatile uint32_t *)0xfec00000;
  81         volatile uint32_t *ioapic_data = (volatile uint32_t *)0xfec00010;
  82
  83         /* Set ACPI base address (I/O space). */
  84         pci_write_config32(dev, PMBASE, (PMBASE_ADDR | 1));
  85
  86         /* Enable ACPI I/O and power management. */
  87         pci_write_config8(dev, ACPI_CNTL, 0x10);
  88
  89         reg32 = pci_read_config32(dev, GEN_CNTL);
  90         reg32 |= (3 << 7);      /* Enable IOAPIC */
  91         reg32 |= (1 << 13);     /* Coprocessor error enable */
  92         reg32 |= (1 << 1);      /* Delayed transaction enable */
  93         reg32 |= (1 << 2);      /* DMA collection buffer enable */
  94         pci_write_config32(dev, GEN_CNTL, reg32);
  95         printk_debug("IOAPIC Southbridge enabled %x\n", reg32);
  96
  97         *ioapic_index = 0;
  98         *ioapic_data = (1 << 25);
  99
 100         *ioapic_index = 0;
 101         reg32 = *ioapic_data;
 102         printk_debug("Southbridge APIC ID = %x\n", reg32);
 103         if (reg32 != (1 << 25))
 104                 die("APIC Error\n");
 105
 106         /* TODO: From i82801ca, needed/useful on other ICH? */
 107         *ioapic_index = 3; /* Select Boot Configuration register. */
 108         *ioapic_data = 1; /* Use Processor System Bus to deliver interrupts. */
 109 }
 110
 111 void i82801ax_enable_serial_irqs(struct device *dev)
 112 {
 113         /* Set packet length and toggle silent mode bit. */
 114         pci_write_config8(dev, SERIRQ_CNTL,
 115                           (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0));
 116         pci_write_config8(dev, SERIRQ_CNTL,
 117                           (1 << 7) | (0 << 6) | ((21 - 17) << 2) | (0 << 0));
 118         /* TODO: Explain/#define the real meaning of these magic numbers. */
 119 }
 120
 121 static void i82801ax_pirq_init(device_t dev, uint16_t ich_model)
 122 {
 123         /* Get the chip configuration */
 124         config_t *config = dev->chip_info;
 125
 126         if (config->pirqa_routing) {
 127                 pci_write_config8(dev, PIRQA_ROUT, config->pirqa_routing);
 128         } else {
 129                 pci_write_config8(dev, PIRQA_ROUT, PIRQA);
 130         }
 131
 132         if (config->pirqb_routing) {
 133                 pci_write_config8(dev, PIRQB_ROUT, config->pirqb_routing);
 134         } else {
 135                 pci_write_config8(dev, PIRQB_ROUT, PIRQB);
 136         }
 137
 138         if (config->pirqc_routing) {
 139                 pci_write_config8(dev, PIRQC_ROUT, config->pirqc_routing);
 140         } else {
 141                 pci_write_config8(dev, PIRQC_ROUT, PIRQC);
 142         }
 143
 144         if (config->pirqd_routing) {
 145                 pci_write_config8(dev, PIRQD_ROUT, config->pirqd_routing);
 146         } else {
 147                 pci_write_config8(dev, PIRQD_ROUT, PIRQD);
 148         }
 149
 150         /* Route PIRQE - PIRQH (for ICH2-ICH9). */
 151         if (ich_model >= 0x2440) {
 152
 153                 if (config->pirqe_routing) {
 154                         pci_write_config8(dev, PIRQE_ROUT, config->pirqe_routing);
 155                 } else {
 156                         pci_write_config8(dev, PIRQE_ROUT, PIRQE);
 157                 }
 158
 159                 if (config->pirqf_routing) {
 160                         pci_write_config8(dev, PIRQF_ROUT, config->pirqf_routing);
 161                 } else {
 162                         pci_write_config8(dev, PIRQF_ROUT, PIRQF);
 163                 }
 164
 165                 if (config->pirqg_routing) {
 166                         pci_write_config8(dev, PIRQG_ROUT, config->pirqg_routing);
 167                 } else {
 168                         pci_write_config8(dev, PIRQG_ROUT, PIRQG);
 169                 }
 170
 171                 if (config->pirqh_routing) {
 172                         pci_write_config8(dev, PIRQH_ROUT, config->pirqh_routing);
 173                 } else {
 174                         pci_write_config8(dev, PIRQH_ROUT, PIRQH);
 175                 }
 176         }
 177 }
 178
 179 static void i82801ax_power_options(device_t dev)
 180 {
 181         uint8_t byte;
 182         int pwr_on = -1;
 183         int nmi_option;
 184
 185         /* power after power fail */
 186         /* FIXME this doesn't work! */
 187         /* Which state do we want to goto after g3 (power restored)?
 188          * 0 == S0 Full On
 189          * 1 == S5 Soft Off
 190          */
 191         pci_write_config8(dev, GEN_PMCON_3, pwr_on ? 0 : 1);
 192         printk_info("Set power %s if power fails\n", pwr_on ? "on" : "off");
 193
 194         /* Set up NMI on errors. */
 195         byte = inb(0x61);
 196         byte &= ~(1 << 3);      /* IOCHK# NMI Enable */
 197         byte &= ~(1 << 2);      /* PCI SERR# Enable */
 198         outb(byte, 0x61);
 199         byte = inb(0x70);
 200
 201         nmi_option = NMI_OFF;
 202         get_option(&nmi_option, "nmi");
 203         if (nmi_option) {
 204                 byte &= ~(1 << 7);      /* Set NMI. */
 205                 outb(byte, 0x70);
 206         }
 207 }
 208
 209 static void gpio_init(device_t dev, uint16_t ich_model)
 210 {
 211         /* Set the value for GPIO base address register and enable GPIO.
 212          * Note: ICH-ICH5 registers differ from ICH6-ICH9.
 213          */
 214         if (ich_model <= 0x24D0) {
 215                 pci_write_config32(dev, GPIO_BASE_ICH0_5, (GPIO_BASE_ADDR | 1));
 216                 pci_write_config8(dev, GPIO_CNTL_ICH0_5, 0x10);
 217         } else if (ich_model >= 0x2640) {
 218                 pci_write_config32(dev, GPIO_BASE_ICH6_9, (GPIO_BASE_ADDR | 1));
 219                 pci_write_config8(dev, GPIO_CNTL_ICH6_9, 0x10);
 220         }
 221 }
 222
 223 void i82801ax_rtc_init(struct device *dev)
 224 {
 225         uint8_t reg8;
 226         uint32_t reg32;
 227         int rtc_failed;
 228
 229         reg8 = pci_read_config8(dev, GEN_PMCON_3);
 230         rtc_failed = reg8 & RTC_BATTERY_DEAD;
 231         if (rtc_failed) {
 232                 reg8 &= ~(1 << 1);      /* Preserve the power fail state. */
 233                 pci_write_config8(dev, GEN_PMCON_3, reg8);
 234         }
 235         reg32 = pci_read_config32(dev, GEN_STS);
 236         rtc_failed |= reg32 & (1 << 2);
 237         rtc_init(rtc_failed);
 238
 239         /* Enable access to the upper 128 byte bank of CMOS RAM. */
 240         pci_write_config8(dev, RTC_CONF, 0x04);
 241 }
 242
 243 void i82801ax_lpc_route_dma(struct device *dev, uint8_t mask)
 244 {
 245         uint16_t reg16;
 246         int i;
 247
 248         reg16 = pci_read_config16(dev, PCI_DMA_CFG);
 249         reg16 &= 0x300;
 250         for (i = 0; i < 8; i++) {
 251                 if (i == 4)
 252                         continue;
 253                 reg16 |= ((mask & (1 << i)) ? 3 : 1) << (i * 2);
 254         }
 255         pci_write_config16(dev, PCI_DMA_CFG, reg16);
 256 }
 257
 258 static void i82801ax_lpc_decode_en(device_t dev, uint16_t ich_model)
 259 {
 260         /* Decode 0x3F8-0x3FF (COM1) for COMA port, 0x2F8-0x2FF (COM2) for COMB.
 261          * LPT decode defaults to 0x378-0x37F and 0x778-0x77F.
 262          * Floppy decode defaults to 0x3F0-0x3F5, 0x3F7.
 263          * We also need to set the value for LPC I/F Enables Register.
 264          * Note: ICH-ICH5 registers differ from ICH6-ICH9.
 265          */
 266         if (ich_model <= 0x24D0) {
 267                 pci_write_config8(dev, COM_DEC, 0x10);
 268                 pci_write_config16(dev, LPC_EN_ICH0_5, 0x300F);
 269         } else if (ich_model >= 0x2640) {
 270                 pci_write_config8(dev, LPC_IO_DEC, 0x10);
 271                 pci_write_config16(dev, LPC_EN_ICH6_9, 0x300F);
 272         }
 273 }
 274
 275 static void enable_hpet(struct device *dev)
 276 {
 277 #ifdef HPET_PRESENT
 278         uint32_t reg32;
 279         uint32_t code = (0 & 0x3);
 280
 281         reg32 = pci_read_config32(dev, GEN_CNTL);
 282         reg32 |= (1 << 17);     /* Enable HPET. */
 283         /*
 284          * Bits [16:15] Memory Address Range
 285          * 00           FED0_0000h - FED0_03FFh
 286          * 01           FED0_1000h - FED0_13FFh
 287          * 10           FED0_2000h - FED0_23FFh
 288          * 11           FED0_3000h - FED0_33FFh
 289          */
 290         reg32 &= ~(3 << 15);    /* Clear it */
 291         reg32 |= (code << 15);
 292         /* TODO: reg32 is never written to anywhere? */
 293         printk_debug("Enabling HPET @0x%x\n", HPET_ADDR | (code << 12));
 294 #endif
 295 }
 296
 297 static void lpc_init(struct device *dev)
 298 {
 299         uint16_t ich_model = pci_read_config16(dev, PCI_DEVICE_ID);
 300
 301         /* Set the value for PCI command register. */
 302         pci_write_config16(dev, PCI_COMMAND, 0x000f);
 303
 304         /* IO APIC initialization. */
 305         i82801ax_enable_apic(dev);
 306
 307         i82801ax_enable_serial_irqs(dev);
 308
 309         /* Setup the PIRQ. */
 310         i82801ax_pirq_init(dev, ich_model);
 311
 312         /* Setup power options. */
 313         i82801ax_power_options(dev);
 314
 315         /* Set the state of the GPIO lines. */
 316         gpio_init(dev, ich_model);
 317
 318         /* Initialize the real time clock. */
 319         i82801ax_rtc_init(dev);
 320
 321         /* Route DMA. */
 322         i82801ax_lpc_route_dma(dev, 0xff);
 323
 324         /* Initialize ISA DMA. */
 325         isa_dma_init();
 326
 327         /* Setup decode ports and LPC I/F enables. */
 328         i82801ax_lpc_decode_en(dev, ich_model);
 329
 330         /* Initialize the High Precision Event Timers, if present. */
 331         enable_hpet(dev);
 332 }
 333
 334 static void i82801ax_lpc_read_resources(device_t dev)
 335 {
 336         struct resource *res;
 337
 338         /* Get the normal PCI resources of this device. */
 339         pci_dev_read_resources(dev);
 340
 341         /* Add an extra subtractive resource for both memory and I/O. */
 342         res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
 343         res->base = 0;
 344         res->size = 0x1000;
 345         res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
 346                      IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 347
 348         res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
 349         res->base = 0xff800000;
 350         res->size = 0x00800000; /* 8 MB for flash */
 351         res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
 352                      IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 353
 354         res = new_resource(dev, 3); /* IOAPIC */
 355         res->base = 0xfec00000;
 356         res->size = 0x00001000;
 357         res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 358 }
 359
 360 static void i82801ax_lpc_enable_resources(device_t dev)
 361 {
 362         pci_dev_enable_resources(dev);
 363         enable_childrens_resources(dev);
 364 }
 365
 366 static struct device_operations lpc_ops = {
 367         .read_resources         = i82801ax_lpc_read_resources,
 368         .set_resources          = pci_dev_set_resources,
 369         .enable_resources       = i82801ax_lpc_enable_resources,
 370         .init                   = lpc_init,
 371         .scan_bus               = scan_static_bus,
 372         .enable                 = i82801ax_enable,
 373 };
 374
 375 static const struct pci_driver i82801aa_lpc __pci_driver = {
 376         .ops    = &lpc_ops,
 377         .vendor = PCI_VENDOR_ID_INTEL,
 378         .device = 0x2410,
 379 };
 380
 381 static const struct pci_driver i82801ab_lpc __pci_driver = {
 382         .ops    = &lpc_ops,
 383         .vendor = PCI_VENDOR_ID_INTEL,
 384         .device = 0x2420,
 385 };
 386
 387 static const struct pci_driver i82801ba_lpc __pci_driver = {
 388         .ops    = &lpc_ops,
 389         .vendor = PCI_VENDOR_ID_INTEL,
 390         .device = 0x2440,
 391 };
 392
 393 static const struct pci_driver i82801ca_lpc __pci_driver = {
 394         .ops    = &lpc_ops,
 395         .vendor = PCI_VENDOR_ID_INTEL,
 396         .device = 0x2480,
 397 };
 398
 399 static const struct pci_driver i82801db_lpc __pci_driver = {
 400         .ops    = &lpc_ops,
 401         .vendor = PCI_VENDOR_ID_INTEL,
 402         .device = 0x24c0,
 403 };
 404
 405 static const struct pci_driver i82801dbm_lpc __pci_driver = {
 406         .ops    = &lpc_ops,
 407         .vendor = PCI_VENDOR_ID_INTEL,
 408         .device = 0x24cc,
 409 };
 410
 411 /* 82801EB and 82801ER */
 412 static const struct pci_driver i82801ex_lpc __pci_driver = {
 413         .ops    = &lpc_ops,
 414         .vendor = PCI_VENDOR_ID_INTEL,
 415         .device = 0x24d0,
 416 };