2 * This file is part of the coreboot project.
4 * Based on src/southbridge/via/vt8237r/vt8237_fadt.c
6 * Copyright (C) 2004 Nick Barker <nick.barker9@btinternet.com>
7 * Copyright (C) 2007, 2009 Rudolf Marek <r.marek@assembler.cz>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
25 #include <arch/acpi.h>
26 #include <device/device.h>
27 #include <device/pci.h>
28 #include <device/pci_ids.h>
32 * Create the Fixed ACPI Description Tables (FADT) for any board with this SB.
33 * Reference: ACPIspec40a, 5.2.9, page 118
35 void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
37 acpi_header_t *header = &(fadt->header);
40 /* Power management controller */
41 dev = dev_find_device(PCI_VENDOR_ID_INTEL,
42 PCI_DEVICE_ID_INTEL_82371AB_SMB_ACPI, 0);
44 memset((void *) fadt, 0, sizeof(acpi_fadt_t));
45 memcpy(header->signature, "FACP", 4);
48 memcpy(header->oem_id, "CORE ", 6);
49 memcpy(header->oem_table_id, "COREBOOT", 8);
50 memcpy(header->asl_compiler_id, "CORE", 4);
51 header->asl_compiler_revision = 42;
53 fadt->firmware_ctrl = (u32)facs;
54 fadt->dsdt = (u32)dsdt;
55 fadt->preferred_pm_profile = 0; /* unspecified */
57 fadt->smi_cmd = 0; /* smi command port */
58 fadt->acpi_enable = 0; /* acpi enable smi command */
59 fadt->acpi_disable = 0; /* acpi disable smi command */
60 fadt->s4bios_req = 0x0;
61 fadt->pstate_cnt = 0x0;
63 fadt->pm1a_evt_blk = DEFAULT_PMBASE;
64 fadt->pm1b_evt_blk = 0x0;
65 fadt->pm1a_cnt_blk = DEFAULT_PMBASE + PMCNTRL;
66 fadt->pm1b_cnt_blk = 0x0;
68 fadt->pm2_cnt_blk = 0;
69 fadt->pm_tmr_blk = DEFAULT_PMBASE + PMTMR;
70 fadt->gpe0_blk = DEFAULT_PMBASE + GPSTS;
73 fadt->gpe1_blk_len = 0;
75 /* *_len define register width in bytes */
76 fadt->pm1_evt_len = 4;
77 fadt->pm1_cnt_len = 2;
78 fadt->pm2_cnt_len = 0; /* not supported */
80 fadt->gpe0_blk_len = 4;
82 fadt->cst_cnt = 0; /* smi command to indicate c state changed notification */
83 fadt->p_lvl2_lat = 101; /* >100 means c2 not supported */
84 fadt->p_lvl3_lat = 1001; /* >1000 means c3 not supported */
85 fadt->flush_size = 0; /* only needed if cpu wbinvd is broken */
86 fadt->flush_stride = 0;
87 fadt->duty_offset = 1; /* bit 1:3 in PCNTRL reg (pmbase+0x10) */
88 fadt->duty_width = 3; /* this width is in bits */
89 fadt->day_alrm = 0x0d; /* rtc cmos ram offset */
90 fadt->mon_alrm = 0x0; /* not supported */
91 fadt->century = 0x0; /* not supported */
94 * 0 1: We have user-visible legacy devices
96 * 2 0: VGA is ok to probe
97 * 3 1: MSI are not supported
99 fadt->iapc_boot_arch = 0xb;
103 * Processors in new ACPI-compatible systems are required to
104 * support this function and indicate this to OSPM by setting
107 * If set, indicates that the hardware flushes all caches on the
108 * WBINVD instruction and maintains memory coherency, but does
109 * not guarantee the caches are invalidated.
111 * C1 power state (x86 hlt instruction) is supported on all cpus
113 * 0: C2 only on uniprocessor, 1: C2 on uni- and multiprocessor
115 * 0: pwr button is fixed feature
116 * 1: pwr button has control method device if present
118 * 0: sleep button is fixed feature
119 * 1: sleep button has control method device if present
121 * 0: RTC wake status supported in fixed register spce
123 * 1: RTC can wake from S4
125 * 1: pmtimer is 32bit, 0: pmtimer is 24bit
127 * 1: system supports docking station
128 * 10 RESET_REG_SUPPORT
129 * 1: fadt describes reset register for system reset
131 * 1: No expansion possible, sealed case
133 * 1: Video output, keyboard and mouse are not connected
135 * 1: Special processor instruction needs to be executed
136 * after writing SLP_TYP
138 * 1: PM1 regs support PCIEXP_WAKE_(STS|EN), must be set
139 * on platforms with pci express support
140 * 15 USE_PLATFORM_CLOCK
141 * 1: OS should prefer platform clock over processor internal
143 * 16 S4_RTC_STS_VALID
144 * 17 REMOTE_POWER_ON_CAPABLE
145 * 1: platform correctly supports OSPM leaving GPE wake events
146 * armed prior to an S5 transition.
147 * 18 FORCE_APIC_CLUSTER_MODEL
148 * 19 FORCE_APIC_PHYSICAL_DESTINATION_MODE
152 fadt->reset_reg.space_id = 0;
153 fadt->reset_reg.bit_width = 0;
154 fadt->reset_reg.bit_offset = 0;
155 fadt->reset_reg.resv = 0;
156 fadt->reset_reg.addrl = 0x0;
157 fadt->reset_reg.addrh = 0x0;
158 fadt->reset_value = 0;
160 fadt->x_firmware_ctl_l = (u32)facs;
161 fadt->x_firmware_ctl_h = 0;
162 fadt->x_dsdt_l = (u32)dsdt;
165 fadt->x_pm1a_evt_blk.space_id = 1;
166 fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8;
167 fadt->x_pm1a_evt_blk.bit_offset = 0;
168 fadt->x_pm1a_evt_blk.resv = 0;
169 fadt->x_pm1a_evt_blk.addrl = fadt->pm1a_evt_blk;
170 fadt->x_pm1a_evt_blk.addrh = 0x0;
172 fadt->x_pm1b_evt_blk.space_id = 1;
173 fadt->x_pm1b_evt_blk.bit_width = fadt->pm1_evt_len * 8;
174 fadt->x_pm1b_evt_blk.bit_offset = 0;
175 fadt->x_pm1b_evt_blk.resv = 0;
176 fadt->x_pm1b_evt_blk.addrl = fadt->pm1b_evt_blk;
177 fadt->x_pm1b_evt_blk.addrh = 0x0;
179 fadt->x_pm1a_cnt_blk.space_id = 1;
180 fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8;
181 fadt->x_pm1a_cnt_blk.bit_offset = 0;
182 fadt->x_pm1a_cnt_blk.resv = 0;
183 fadt->x_pm1a_cnt_blk.addrl = fadt->pm1a_cnt_blk;
184 fadt->x_pm1a_cnt_blk.addrh = 0x0;
186 fadt->x_pm1b_cnt_blk.space_id = 1;
187 fadt->x_pm1b_cnt_blk.bit_width = fadt->pm1_cnt_len * 8;
188 fadt->x_pm1b_cnt_blk.bit_offset = 0;
189 fadt->x_pm1b_cnt_blk.resv = 0;
190 fadt->x_pm1b_cnt_blk.addrl = fadt->pm1b_cnt_blk;
191 fadt->x_pm1b_cnt_blk.addrh = 0x0;
193 fadt->x_pm2_cnt_blk.space_id = 1;
194 fadt->x_pm2_cnt_blk.bit_width = fadt->pm2_cnt_len * 8;
195 fadt->x_pm2_cnt_blk.bit_offset = 0;
196 fadt->x_pm2_cnt_blk.resv = 0;
197 fadt->x_pm2_cnt_blk.addrl = fadt->pm2_cnt_blk;
198 fadt->x_pm2_cnt_blk.addrh = 0x0;
200 fadt->x_pm_tmr_blk.space_id = 1;
201 fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8;
202 fadt->x_pm_tmr_blk.bit_offset = 0;
203 fadt->x_pm_tmr_blk.resv = 0;
204 fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk;
205 fadt->x_pm_tmr_blk.addrh = 0x0;
207 fadt->x_gpe0_blk.space_id = 1;
208 fadt->x_gpe0_blk.bit_width = fadt->gpe0_blk_len * 8;
209 fadt->x_gpe0_blk.bit_offset = 0;
210 fadt->x_gpe0_blk.resv = 0;
211 fadt->x_gpe0_blk.addrl = fadt->gpe0_blk;
212 fadt->x_gpe0_blk.addrh = 0x0;
214 fadt->x_gpe1_blk.space_id = 1;
215 fadt->x_gpe1_blk.bit_width = fadt->gpe1_blk_len * 8;;
216 fadt->x_gpe1_blk.bit_offset = 0;
217 fadt->x_gpe1_blk.resv = 0;
218 fadt->x_gpe1_blk.addrl = fadt->gpe1_blk;
219 fadt->x_gpe1_blk.addrh = 0x0;
221 header->checksum = acpi_checksum((void *) fadt, sizeof(acpi_fadt_t));