2 * This file is part of the coreboot project.
4 * Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
23 #include <arch/romcc_io.h>
24 #include <console/console.h>
25 #include <device/pci_ids.h>
26 #include <device/pci_def.h>
28 #include "i82371eb_smbus.h"
30 void enable_smbus(void)
36 /* Get the SMBus/PM device of the 82371AB/EB/MB. */
37 dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_INTEL,
38 PCI_DEVICE_ID_INTEL_82371AB_SMB_ACPI), 0);
40 /* Set the SMBus I/O base. */
41 pci_write_config32(dev, SMBBA, SMBUS_IO_BASE | 1);
43 /* Enable the SMBus controller host interface. */
44 reg8 = pci_read_config8(dev, SMBHSTCFG);
46 pci_write_config8(dev, SMBHSTCFG, reg8);
48 /* Enable access to the SMBus I/O space. */
49 reg16 = pci_read_config16(dev, PCI_COMMAND);
50 reg16 |= PCI_COMMAND_IO;
51 pci_write_config16(dev, PCI_COMMAND, reg16);
53 /* Clear any lingering errors, so the transaction will run. */
54 outb(inb(SMBUS_IO_BASE + SMBHST_STATUS), SMBUS_IO_BASE + SMBHST_STATUS);
57 int smbus_read_byte(u8 device, u8 address)
59 return do_smbus_read_byte(SMBUS_IO_BASE, device, address);