2 * This file is part of the coreboot project.
4 * Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 #ifndef SOUTHBRIDGE_INTEL_I82371EB_CHIP_H
22 #define SOUTHBRIDGE_INTEL_I82371EB_CHIP_H
24 #include <device/device.h>
26 extern const struct chip_operations southbridge_intel_i82371eb_ops;
28 struct southbridge_intel_i82371eb_config {
30 int ide0_drive0_udma33_enable:1;
31 int ide0_drive1_udma33_enable:1;
33 int ide1_drive0_udma33_enable:1;
34 int ide1_drive1_udma33_enable:1;
35 int ide_legacy_enable:1;
38 u32 gpo; /* gpio output default */
43 #endif /* SOUTHBRIDGE_INTEL_I82371EB_CHIP_H */