2 * This file is part of the coreboot project.
4 * Copyright (C) 2008 Arastra, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 /* This code is based on src/southbridge/intel/esb6300/esb6300_sata.c */
23 #include <console/console.h>
24 #include <device/device.h>
25 #include <device/pci.h>
26 #include <device/pci_ids.h>
27 #include <device/pci_ops.h>
32 #define SATA_PTIM 0x40
33 #define SATA_STIM 0x42
34 #define SATA_D1TIM 0x44
35 #define SATA_SYNCC 0x48
36 #define SATA_SYNCTIM 0x4A
37 #define SATA_IIOC 0x54
40 #define SATA_ACR0 0xA8
41 #define SATA_ACR1 0xAC
46 typedef struct southbridge_intel_i3100_config config_t;
48 static void sata_init(struct device *dev)
52 /* Get the chip configuration */
53 ahci = (pci_read_config8(dev, SATA_MAP) >> 6) & 0x03;
55 /* Enable SATA devices */
56 printk(BIOS_INFO, "SATA init (%s mode)\n", ahci ? "AHCI" : "Legacy");
60 pci_write_config8(dev, SATA_MAP, (1 << 6) | (0 << 0));
63 pci_write_config8(dev, SATA_PCS, 0x03);
64 pci_write_config8(dev, SATA_PCS + 1, 0x0F);
67 pci_write_config16(dev, SATA_PTIM, 0x8000);
68 pci_write_config16(dev, SATA_STIM, 0x8000);
71 pci_write_config8(dev, SATA_SYNCC, 0);
72 pci_write_config16(dev, SATA_SYNCTIM, 0);
74 /* IDE I/O configuration */
75 pci_write_config32(dev, SATA_IIOC, 0);
78 /* SATA configuration */
79 pci_write_config8(dev, SATA_CMD, 0x07);
80 pci_write_config8(dev, SATA_PI, 0x8f);
83 pci_write_config16(dev, SATA_PTIM, 0x0a307);
84 pci_write_config16(dev, SATA_STIM, 0x0a307);
87 pci_write_config8(dev, SATA_SYNCC, 0x0f);
88 pci_write_config16(dev, SATA_SYNCTIM, 0x1111);
91 pci_write_config16(dev, SATA_IIOC, 0x1000);
94 pci_write_config8(dev, SATA_MAP, 0x00);
96 /* Enable ports 0-3 */
97 pci_write_config8(dev, SATA_PCS + 1, 0x0f);
100 printk(BIOS_DEBUG, "SATA Enabled\n");
103 static void sata_set_subsystem(device_t dev, unsigned vendor, unsigned device)
105 pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
106 ((device & 0xffff) << 16) | (vendor & 0xffff));
109 static struct pci_operations lops_pci = {
110 .set_subsystem = sata_set_subsystem,
113 static struct device_operations sata_ops = {
114 .read_resources = pci_dev_read_resources,
115 .set_resources = pci_dev_set_resources,
116 .enable_resources = pci_dev_enable_resources,
119 .enable = i3100_enable,
120 .ops_pci = &lops_pci,
123 static const struct pci_driver ide_driver __pci_driver = {
125 .vendor = PCI_VENDOR_ID_INTEL,
126 .device = PCI_DEVICE_ID_INTEL_3100_IDE,
129 static const struct pci_driver sata_driver __pci_driver = {
131 .vendor = PCI_VENDOR_ID_INTEL,
132 .device = PCI_DEVICE_ID_INTEL_3100_AHCI,
135 static const struct pci_driver ide_driver_ep80579 __pci_driver = {
137 .vendor = PCI_VENDOR_ID_INTEL,
138 .device = PCI_DEVICE_ID_INTEL_EP80579_IDE,
141 static const struct pci_driver sata_driver_ep80579 __pci_driver = {
143 .vendor = PCI_VENDOR_ID_INTEL,
144 .device = PCI_DEVICE_ID_INTEL_EP80579_AHCI,