2 * This file is part of the coreboot project.
4 * Copyright (C) 2008 Arastra, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 static void i3100_enable_superio(void)
23 device_t dev = PCI_DEV(0x0, 0x1f, 0x0);
25 /* Enable decoding of I/O locations for SuperIO devices */
26 pci_write_config16(dev, 0x80, 0x0010);
27 pci_write_config16(dev, 0x82, 0x340f);
29 /* Enable the SERIRQs (start pulse width is 8 clock cycles) */
30 pci_write_config8(dev, 0x64, 0xD2);
33 static void i3100_halt_tco_timer(void)
35 device_t dev = PCI_DEV(0x0, 0x1f, 0x0);
37 /* Temporarily enable the ACPI I/O range at 0x4000 */
38 pci_write_config32(dev, 0x40, 0x4000 | (1 << 0));
39 pci_write_config32(dev, 0x44, pci_read_config32(dev, 0x44) | (1 << 7));
41 /* Halt the TCO timer, preventing SMI and automatic reboot */
42 outw(inw(0x4068) | (1 << 11), 0x4068);
44 /* Disable the ACPI I/O range */
45 pci_write_config32(dev, 0x44, pci_read_config32(dev, 0x44) & ~(1 << 7));