2 * This file is part of the coreboot project.
4 * Copyright (C) 2008 Arastra, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 struct southbridge_intel_i3100_config
23 #define I3100_GPIO_USE_MASK 0x03
24 #define I3100_GPIO_USE_DEFAULT 0x00
25 #define I3100_GPIO_USE_AS_NATIVE 0x01
26 #define I3100_GPIO_USE_AS_GPIO 0x02
28 #define I3100_GPIO_SEL_MASK 0x0c
29 #define I3100_GPIO_SEL_DEFAULT 0x00
30 #define I3100_GPIO_SEL_OUTPUT 0x04
31 #define I3100_GPIO_SEL_INPUT 0x08
33 #define I3100_GPIO_LVL_MASK 0x30
34 #define I3100_GPIO_LVL_DEFAULT 0x00
35 #define I3100_GPIO_LVL_LOW 0x10
36 #define I3100_GPIO_LVL_HIGH 0x20
37 #define I3100_GPIO_LVL_BLINK 0x30
39 #define I3100_GPIO_INV_MASK 0xc0
40 #define I3100_GPIO_INV_DEFAULT 0x00
41 #define I3100_GPIO_INV_OFF 0x40
42 #define I3100_GPIO_INV_ON 0x80
46 int sata_ports_implemented;
50 extern struct chip_operations southbridge_intel_i3100_ops;