src/southbridge/intel/esb6300/esb6300_bridge1c.c

   1 #include <console/console.h>
   2 #include <device/device.h>
   3 #include <device/pci.h>
   4 #include <device/pci_ids.h>
   5 #include <device/pci_ops.h>
   6 #include "esb6300.h"
   7
   8 static void bridge1c_init(struct device *dev)
   9 {
  10
  11         uint16_t word;
  12
  13         /* configuration */
  14         pci_write_config8(dev, 0x1b, 0x30);
  15 //      pci_write_config8(dev, 0x3e, 0x07);
  16         pci_write_config8(dev, 0x3e, 0x04);  /* parity ignore */
  17         pci_write_config8(dev, 0x6c, 0x0c);  /* undocumented  */
  18         pci_write_config8(dev, 0xe0, 0x20);
  19
  20         /* SRB enable */
  21         pci_write_config16(dev, 0xe4, 0x0232);
  22
  23         /* Burst size */
  24         pci_write_config8(dev, 0xf0, 0x02);
  25
  26         /* prefetch threshold size */
  27         pci_write_config16(dev, 0xf8, 0x2121);
  28
  29         /* primary latency */
  30         pci_write_config8(dev, 0x0d, 0x28);
  31
  32         /* multi transaction timer */
  33         pci_write_config8(dev, 0x42, 0x08);
  34
  35 }
  36
  37 static struct device_operations pci_ops  = {
  38         .read_resources   = pci_bus_read_resources,
  39         .set_resources    = pci_dev_set_resources,
  40         .enable_resources = pci_bus_enable_resources,
  41         .init             = bridge1c_init,
  42         .scan_bus         = pci_scan_bridge,
  43         .ops_pci          = 0,
  44 };
  45
  46 static const struct pci_driver pci_driver __pci_driver = {
  47         .ops    = &pci_ops,
  48         .vendor = PCI_VENDOR_ID_INTEL,
  49         .device = PCI_DEVICE_ID_INTEL_6300ESB_PCI_X,
  50 };
  51