first round name simplification. drop the <component>_ prefix.
[coreboot.git] / src / southbridge / broadcom / bcm5785 / lpc.c
1 /*
2  * This file is part of the coreboot project.
3  *
4  * Copyright (C) 2005 AMD
5  * Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License as published by
9  * the Free Software Foundation; version 2 of the License.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  *
16  * You should have received a copy of the GNU General Public License
17  * along with this program; if not, write to the Free Software
18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
19  */
20
21 #include <console/console.h>
22 #include <device/device.h>
23 #include <device/pci.h>
24 #include <device/pnp.h>
25 #include <device/pci_ids.h>
26 #include <device/pci_ops.h>
27 #include <pc80/mc146818rtc.h>
28 #include <pc80/isa-dma.h>
29 #include <bitops.h>
30 #include <arch/io.h>
31 #include <arch/ioapic.h>
32 #include "bcm5785.h"
33
34 static void lpc_init(device_t dev)
35 {
36         /* Initialize the real time clock */
37         rtc_init(0);
38
39         /* Initialize isa dma */
40         isa_dma_init();
41 }
42
43 static void bcm5785_lpc_read_resources(device_t dev)
44 {
45         struct resource *res;
46
47         /* Get the normal pci resources of this device */
48         pci_dev_read_resources(dev);
49
50         /* Add an extra subtractive resource for both memory and I/O. */
51         res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
52         res->base = 0;
53         res->size = 0x1000;
54         res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
55                      IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
56
57         res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
58         res->base = 0xff800000;
59         res->size = 0x00800000; /* 8 MB for flash */
60         res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
61                      IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
62
63         res = new_resource(dev, 3); /* IOAPIC */
64         res->base = IO_APIC_ADDR;
65         res->size = 0x00001000;
66         res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
67 }
68
69 /**
70  * Enable resources for children devices.
71  *
72  * @param dev The device whos children's resources are to be enabled.
73  */
74 static void bcm5785_lpc_enable_childrens_resources(device_t dev)
75 {
76         struct bus *link;
77         uint32_t reg;
78
79         reg = pci_read_config8(dev, 0x44);
80
81         for (link = dev->link_list; link; link = link->next) {
82                 device_t child;
83                 for (child = link->children; child; child = child->sibling) {
84                         if(child->enabled && (child->path.type == DEVICE_PATH_PNP)) {
85                                 struct resource *res;
86                                 for(res = child->resource_list; res; res = res->next) {
87                                         unsigned long base, end; // don't need long long
88                                         if(!(res->flags & IORESOURCE_IO)) continue;
89                                         base = res->base;
90                                         end = resource_end(res);
91                                         printk(BIOS_DEBUG, "bcm5785lpc decode:%s, base=0x%08lx, end=0x%08lx\n",dev_path(child),base, end);
92                                         switch(base) {
93                                         case 0x60: //KBC
94                                         case 0x64:
95                                                 reg |= (1<<29);
96                                         case 0x3f8: // COM1
97                                                 reg |= (1<<6);  break;
98                                         case 0x2f8: // COM2
99                                                 reg |= (1<<7);  break;
100                                         case 0x378: // Parallal 1
101                                                 reg |= (1<<0); break;
102                                         case 0x3f0: // FD0
103                                                 reg |= (1<<26); break;
104                                         case 0x220:  // Aduio 0
105                                                 reg |= (1<<14); break;
106                                         case 0x300:  // Midi 0
107                                                 reg |= (1<<18); break;
108                                         }
109                                 }
110                         }
111                 }
112         }
113         pci_write_config32(dev, 0x44, reg);
114
115
116 }
117
118 static void bcm5785_lpc_enable_resources(device_t dev)
119 {
120         pci_dev_enable_resources(dev);
121         bcm5785_lpc_enable_childrens_resources(dev);
122 }
123
124 static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
125 {
126         pci_write_config32(dev, 0x40,
127                 ((device & 0xffff) << 16) | (vendor & 0xffff));
128 }
129
130 static struct pci_operations lops_pci = {
131         .set_subsystem = lpci_set_subsystem,
132 };
133
134 static struct device_operations lpc_ops  = {
135         .read_resources   = bcm5785_lpc_read_resources,
136         .set_resources    = pci_dev_set_resources,
137         .enable_resources = bcm5785_lpc_enable_resources,
138         .init             = lpc_init,
139         .scan_bus         = scan_static_bus,
140 //      .enable           = bcm5785_enable,
141         .ops_pci          = &lops_pci,
142 };
143
144 static const struct pci_driver lpc_driver __pci_driver = {
145         .ops    = &lpc_ops,
146         .vendor = PCI_VENDOR_ID_SERVERWORKS,
147         .device = PCI_DEVICE_ID_SERVERWORKS_BCM5785_LPC,
148 };