3 * by yinghai.lu@amd.com
8 #define PCI_DEV(BUS, DEV, FN) ( \
9 (((BUS) & 0xFFF) << 20) | \
10 (((DEV) & 0x1F) << 15) | \
13 typedef unsigned device_t;
15 static void pci_write_config32(device_t dev, unsigned where, unsigned value)
18 addr = (dev>>4) | where;
19 outl(0x80000000 | (addr & ~3), 0xCF8);
23 static unsigned pci_read_config32(device_t dev, unsigned where)
26 addr = (dev>>4) | where;
27 outl(0x80000000 | (addr & ~3), 0xCF8);
31 #include "../../../northbridge/amd/amdk8/reset_test.c"
36 /* Try rebooting through port 0xcf9 */
37 /* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */
38 outb((0 <<3)|(0<<2)|(1<<1), 0xcf9);
39 outb((0 <<3)|(1<<2)|(1<<1), 0xcf9);