2 * This file is part of the coreboot project.
4 * Copyright (C) 2010 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 #include <console/console.h>
21 #include <device/device.h>
22 #include <device/pci.h>
23 #include <device/pci_ids.h>
24 #include <device/pci_ops.h>
29 /*------------------------------------------------
31 ------------------------------------------------*/
32 PCIE_CFG AtiPcieCfg = {
33 PCIE_ENABLE_STATIC_DEV_REMAP, /* Config */
34 0, /* ResetReleaseDelay */
39 0, /* PortDetect, filled by GppSbInit */
52 static void ValidatePortEn(device_t nb_dev);
54 static void ValidatePortEn(device_t nb_dev)
58 /*****************************************************************
59 * Compliant with CIM_33's PCIEPowerOffGppPorts
60 * Power off unused GPP lines
61 *****************************************************************/
62 static void PciePowerOffGppPorts(device_t nb_dev, device_t dev, u32 port)
66 struct southbridge_amd_sr5650_config *cfg =
67 (struct southbridge_amd_sr5650_config *)nb_dev->chip_info;
68 u16 state = cfg->port_enable;
70 if (!(AtiPcieCfg.Config & PCIE_DISABLE_HIDE_UNUSED_PORTS))
71 state &= AtiPcieCfg.PortDetect;
73 state &= (1 << 4) + (1 << 5) + (1 << 6) + (1 << 7);
74 state_save = state << 17;
75 state &= !(AtiPcieCfg.PortHp);
76 reg = nbmisc_read_index(nb_dev, 0x0c);
78 nbmisc_write_index(nb_dev, 0x0c, reg);
80 reg = nbmisc_read_index(nb_dev, 0x08);
82 nbmisc_write_index(nb_dev, 0x08, reg);
84 if ((AtiPcieCfg.Config & PCIE_OFF_UNUSED_GPP_LANES)
86 Config & (PCIE_DISABLE_HIDE_UNUSED_PORTS +
87 PCIE_GFX_COMPLIANCE))) {
89 /* step 3 Power Down Control for Southbridge */
90 reg = nbpcie_p_read_index(dev, 0xa2);
92 switch ((reg >> 4) & 0x7) { /* get bit 4-6, LC_LINK_WIDTH_RD */
94 nbpcie_ind_write_index(nb_dev, 0x65, 0x0e0e);
97 nbpcie_ind_write_index(nb_dev, 0x65, 0x0c0c);
104 /**********************************************************************
105 **********************************************************************/
106 static void switching_gpp1_configurations(device_t nb_dev, device_t sb_dev)
109 struct southbridge_amd_sr5650_config *cfg =
110 (struct southbridge_amd_sr5650_config *)nb_dev->chip_info;
112 /* 4.3.3.1.1.1.step1. Asserts PCIE-GPP1 global reset */
113 reg = nbmisc_read_index(nb_dev, 0x8);
115 nbmisc_write_index(nb_dev, 0x8, reg);
117 /* 4.3.3.1.1.1.step2. De-asserts STRAP_BIF_all_valid for PCIE-GPP1 core */
118 reg = nbmisc_read_index(nb_dev, 0x26);
120 nbmisc_write_index(nb_dev, 0x26, reg);
122 /* 4.3.3.1.1.1.step3. Programs PCIE-GPP1 to be desired port configuration 8:8 or 16:0. */
123 reg = nbmisc_read_index(nb_dev, 0x8);
124 reg &= ~(1 << 8); /* clean */
125 reg |= cfg->gpp1_configuration << 8;
126 nbmisc_write_index(nb_dev, 0x8, reg);
128 /* 4.3.3.1.1.1.step4. Wait for 2ms */
131 /* 4.3.3.1.1.1.step5. Asserts STRAP_BIF_all_valid for PCIE-GPP1 core */
132 reg = nbmisc_read_index(nb_dev, 0x26);
134 nbmisc_write_index(nb_dev, 0x26, reg);
136 /* 4.3.3.1.1.1.step6. De-asserts PCIE-GPP1 global reset */
137 reg = nbmisc_read_index(nb_dev, 0x8);
139 nbmisc_write_index(nb_dev, 0x8, reg);
141 /* Follow the procedure for PCIE-GPP1 common initialization and
142 * link training sequence. */
145 /**********************************************************************
146 **********************************************************************/
147 static void switching_gpp2_configurations(device_t nb_dev, device_t sb_dev)
150 struct southbridge_amd_sr5650_config *cfg =
151 (struct southbridge_amd_sr5650_config *)nb_dev->chip_info;
153 /* 4.3.3.1.1.2.step1. Asserts PCIE-GPP2 global reset */
154 reg = nbmisc_read_index(nb_dev, 0x8);
156 nbmisc_write_index(nb_dev, 0x8, reg);
158 /* 4.3.3.1.1.2.step2. De-asserts STRAP_BIF_all_valid for PCIE-GPP2 core */
159 reg = nbmisc_read_index(nb_dev, 0x26);
161 nbmisc_write_index(nb_dev, 0x26, reg);
163 /* 4.3.3.1.1.2.step3. Programs PCIE-GPP2 to be desired port configuration 8:8 or 16:0. */
164 reg = nbmisc_read_index(nb_dev, 0x8);
165 reg &= ~(1 << 9); /* clean */
166 reg |= (cfg->gpp2_configuration & 1) << 9;
167 nbmisc_write_index(nb_dev, 0x8, reg);
169 /* 4.3.3.1.1.2.step4. Wait for 2ms */
172 /* 4.3.3.1.1.2.step5. Asserts STRAP_BIF_all_valid for PCIE-GPP2 core */
173 reg = nbmisc_read_index(nb_dev, 0x26);
175 nbmisc_write_index(nb_dev, 0x26, reg);
177 /* 4.3.3.1.1.2.step6. De-asserts PCIE-GPP2 global reset */
178 reg = nbmisc_read_index(nb_dev, 0x8);
180 nbmisc_write_index(nb_dev, 0x8, reg);
182 /* Follow the procedure for PCIE-GPP2 common initialization and
183 * link training sequence. */
185 static void switching_gpp3a_configurations(device_t nb_dev, device_t sb_dev)
188 struct southbridge_amd_sr5650_config *cfg =
189 (struct southbridge_amd_sr5650_config *)nb_dev->chip_info;
191 /* 4.3.3.2.3.2.step1. Asserts PCIE-GPP3a global reset. */
192 reg = nbmisc_read_index(nb_dev, 0x8);
194 nbmisc_write_index(nb_dev, 0x8, reg);
195 /* 4.3.3.2.3.2.step2. De-asserts STRAP_BIF_all_valid for PCIE-GPP3a core */
196 reg = nbmisc_read_index(nb_dev, 0x26);
198 nbmisc_write_index(nb_dev, 0x26, reg);
199 /* 4.3.3.2.3.2.step3. Programs the desired PCIE-GPP3a configuration. */
200 reg = nbmisc_read_index(nb_dev, 0x67);
201 reg &= ~0x1F; /* clean */
202 reg |= cfg->gpp3a_configuration;
203 nbmisc_write_index(nb_dev, 0x67, reg);
204 /* 4.3.3.2.3.2.step4. Programs PCIE-GPP3a Line Director. */
205 reg = nbmisc_read_index(nb_dev, 0x26);
206 reg &= 0xF0000000; /* TODO:Lane reversed. */
207 switch (cfg->gpp3a_configuration) {
208 case 0xB: /* 1:1:1:1:1:1 */
211 case 0x1: /* 4:2:0:0:0:0 */
214 case 0x2: /* 4:1:1:0:0:0 */
217 case 0xC: /* 2:2:2:0:0:0 */
220 case 0xA: /* 2:2:1:1:0:0 */
223 case 0x4: /* 2:1:1:1:1:0 */
226 default: /* shouldn't be here. */
227 printk(BIOS_DEBUG, "Warning:gpp3a_configuration is not correct. Check you devicetree.cb\n");
230 nbmisc_write_index(nb_dev, 0x26, reg);
231 /* 4.3.3.2.3.2.step5. De-asserts STRAP_BIF_all_valid for PCIE-GPP3a core */
232 reg = nbmisc_read_index(nb_dev, 0x26);
234 nbmisc_write_index(nb_dev, 0x26, reg);
235 /* 4.3.3.2.3.2.step6. De-asserts PCIE-GPP3a global reset. */
236 reg = nbmisc_read_index(nb_dev, 0x8);
238 nbmisc_write_index(nb_dev, 0x8, reg);
241 /*****************************************************************
242 * The sr5650 uses NBCONFIG:0x1c (BAR3) to map the PCIE Extended Configuration
243 * Space to a 256MB range within the first 4GB of addressable memory.
244 *****************************************************************/
245 void enable_pcie_bar3(device_t nb_dev)
247 printk(BIOS_DEBUG, "enable_pcie_bar3()\n");
248 set_nbcfg_enable_bits(nb_dev, 0x7C, 1 << 30, 1 << 30); /* Enables writes to the BAR3 register. */
249 set_nbcfg_enable_bits(nb_dev, 0x84, 7 << 16, 0 << 16);
251 pci_write_config32(nb_dev, 0x1C, EXT_CONF_BASE_ADDRESS); /* PCIEMiscInit */
252 pci_write_config32(nb_dev, 0x20, 0x00000000);
253 set_htiu_enable_bits(nb_dev, 0x32, 1 << 28, 1 << 28); /* PCIEMiscInit */
254 ProgK8TempMmioBase(1, EXT_CONF_BASE_ADDRESS, TEMP_MMIO_BASE_ADDRESS);
257 /*****************************************************************
258 * We should disable bar3 when we want to exit sr5650_enable, because bar3 will be
259 * remapped in set_resource later.
260 *****************************************************************/
261 void disable_pcie_bar3(device_t nb_dev)
263 printk(BIOS_DEBUG, "disable_pcie_bar3()\n");
264 pci_write_config32(nb_dev, 0x1C, 0); /* clear BAR3 address */
265 set_nbcfg_enable_bits(nb_dev, 0x7C, 1 << 30, 0 << 30); /* Disable writes to the BAR3. */
266 ProgK8TempMmioBase(0, EXT_CONF_BASE_ADDRESS, TEMP_MMIO_BASE_ADDRESS);
270 * GEN2 Software Compliance
272 void init_gen2(device_t nb_dev, device_t dev, u8 port)
276 /* for A11 (0x89 == 0) */
286 /* TODO: check for rev > a11 */
320 /* Enables GEN2 capability of the device */
321 set_pcie_enable_bits(dev, 0xA4, 0x1, 0x1);
322 /* Advertise the link speed to be Gen2 */
323 pci_ext_write_config32(nb_dev, dev, 0x88, 0xF0, 1<<2); /* LINK_CRTL2 */
324 set_nbmisc_enable_bits(nb_dev, reg, val, val);
328 /* Alternative to default CPL buffer count */
329 const u8 pGpp420000[] = {0x38, 0x1C};
330 const u8 pGpp411000[] = {0x38, 0x0E, 0x0E};
331 const u8 pGpp222000[] = {0x1C, 0x1C, 0x1C};
332 const u8 pGpp221100[] = {0x1C, 0x1C, 0x0E, 0x0E};
333 const u8 pGpp211110[] = {0x1C, 0x0E, 0x0E, 0x0E, 0, 0x0E, 0x0E};
334 const u8 pGpp111111[] = {0x0E, 0x0E, 0x0E, 0x0E, 0, 0x0E, 0x0E};
337 * Enabling Dynamic Slave CPL Buffer Allocation Feature for PCIE-GPP3a Ports
338 * PcieLibCplBufferAllocation
340 static void gpp3a_cpl_buf_alloc(device_t nb_dev, device_t dev)
345 struct southbridge_amd_sr5650_config *cfg =
346 (struct southbridge_amd_sr5650_config *)nb_dev->chip_info;
348 dev_index = dev->path.pci.devfn >> 3;
349 if (dev_index < 4 || dev_index > 0xa) {
353 switch (cfg->gpp3a_configuration) {
354 case 0x1: /* 4:2:0:0:0:0 */
355 slave_cpl = (u8 *)&pGpp420000;
357 case 0x2: /* 4:1:1:0:0:0 */
358 slave_cpl = (u8 *)&pGpp411000;
360 case 0xC: /* 2:2:2:0:0:0 */
361 slave_cpl = (u8 *)&pGpp222000;
363 case 0xA: /* 2:2:1:1:0:0 */
364 slave_cpl = (u8 *)&pGpp221100;
366 case 0x4: /* 2:1:1:1:1:0 */
367 slave_cpl = (u8 *)&pGpp211110;
369 case 0xB: /* 1:1:1:1:1:1 */
370 slave_cpl = (u8 *)&pGpp111111;
372 default: /* shouldn't be here. */
373 printk(BIOS_WARNING, "buggy gpp3a_configuration\n");
377 value = slave_cpl[dev_index - 4];
379 set_pcie_enable_bits(dev, 0x10, 0x3f << 8, value << 8);
380 set_pcie_enable_bits(dev, 0x20, 1 << 11, 1 << 11);
385 * Enabling Dynamic Slave CPL Buffer Allocation Feature for PCIE-GPP1/PCIE-GPP2 Ports
386 * PcieLibCplBufferAllocation
388 static void gpp12_cpl_buf_alloc(device_t nb_dev, device_t dev)
394 dev_index = dev->path.pci.devfn >> 3;
395 struct southbridge_amd_sr5650_config *cfg =
396 (struct southbridge_amd_sr5650_config *)nb_dev->chip_info;
399 gpp_cfg = cfg->gpp1_configuration;
400 } else if (dev_index > 0xa) {
401 gpp_cfg = cfg->gpp2_configuration;
407 /* Configuration 16:0, leave the default value */
408 } else if (gpp_cfg == 1) {
409 /* Configuration 8:8 */
411 set_pcie_enable_bits(dev, 0x10, 0x3f << 8, value << 8);
412 set_pcie_enable_bits(dev, 0x20, 1 << 11, 1 << 11);
414 printk(BIOS_DEBUG, "buggy gpp configuration\n");
418 #if 1 /* BTS report error without this function. But some board
419 * fail to boot. Leave it here for future debug. */
422 * Enable LCLK clock gating
424 static void EnableLclkGating(device_t dev)
430 device_t nb_dev = dev_find_slot(0, 0);
431 device_t clk_f1= dev_find_slot(0, 1);
434 port = dev->path.pci.devfn >> 3;
436 //PCIE_CORE_INDEX_GPP1
443 //PCIE_CORE_INDEX_GPP2
449 //PCIE_CORE_INDEX_GPP3a
456 //PCIE_CORE_INDEX_GPP3b;
461 //PCIE_CORE_INDEX_SB;
469 /* enable access func1 */
470 set_nbcfg_enable_bits(nb_dev, 0x4C, 1 << 0, 1 << 0);
471 set_nbcfg_enable_bits(clk_f1, reg, mask, value);
475 /*****************************************
476 * Compliant with CIM_33's PCIEGPPInit
482 * p2p bridge number, 4-10
483 *****************************************/
484 void sr5650_gpp_sb_init(device_t nb_dev, device_t dev, u32 port)
487 struct southbridge_amd_sr5650_config *cfg =
488 (struct southbridge_amd_sr5650_config *)nb_dev->chip_info;
490 printk(BIOS_DEBUG, "gpp_sb_init nb_dev=0x%p, dev=0x%p, port=0x%x\n", nb_dev, dev, port);
494 gpp_sb_sel = PCIE_CORE_INDEX_GPP1;
499 gpp_sb_sel = PCIE_CORE_INDEX_GPP3a;
502 gpp_sb_sel = PCIE_CORE_INDEX_SB;
506 gpp_sb_sel = PCIE_CORE_INDEX_GPP2;
509 gpp_sb_sel = PCIE_CORE_INDEX_GPP3b;
513 /* Init common Core registers */
514 set_pcie_enable_bits(dev, 0xB1, 1 << 28 | 1 << 23 | 1 << 20 | 1 << 19,
515 1 << 28 | 1 << 23 | 1 << 20 | 1 << 19);
516 if (gpp_sb_sel == PCIE_CORE_INDEX_GPP3a) {
517 set_pcie_enable_bits(dev, 0xB1, 1 << 22, 1 << 22);
518 /* 4.3.3.2.3 Step 10: Dynamic Slave CPL Buffer Allocation */
519 gpp3a_cpl_buf_alloc(nb_dev, dev);
521 if (gpp_sb_sel == PCIE_CORE_INDEX_GPP1 || gpp_sb_sel == PCIE_CORE_INDEX_GPP2) {
522 gpp12_cpl_buf_alloc(nb_dev, dev);
524 set_pcie_enable_bits(dev, 0xA1, (1 << 26) | (1 << 24) | (1 << 11), 1 << 11);
525 set_pcie_enable_bits(dev, 0xA0, 0x0000FFF0, 0x6830);
526 // PCIE should not ignore malformed packet error or ATS request
527 set_pcie_enable_bits(dev, 0x70, 1 << 12, 0);
528 //Step 14.1: Advertising Hot Plug Capabilities
529 set_pcie_enable_bits(dev, 0x10, 1 << 4, 1 << 4); //Enable power fault
531 set_pcie_enable_bits(nb_dev, 0xC1 | gpp_sb_sel, 1 << 0, 1 << 0);
534 /* 4.4.2.step13.1. Sets RCB completion timeout to be 200ms */
535 pci_ext_write_config32(nb_dev, dev, 0x80, 0xF << 0, 0x6 << 0);
536 /* 4.4.2.step13.2. RCB completion timeout on link down to shorten enumeration time. */
537 set_pcie_enable_bits(dev, 0x70, 1 << 19, 1 << 19);
538 /* 4.4.2.step13.3. Enable slave ordering rules */
539 set_pcie_enable_bits(nb_dev, 0x20 | gpp_sb_sel, 1 << 8, 0 << 8);
540 /* 4.4.2.step13.4. Sets DMA payload size to 64 bytes. */
541 set_pcie_enable_bits(nb_dev, 0x10 | gpp_sb_sel, 7 << 10, 4 << 10);
542 /* 4.4.2.step13.5. Set REGS_DLP_IGNORE_IN_L1_EN to ignore DLLPs
543 during L1 so that Tx Clk can be turned off. */
544 set_pcie_enable_bits(nb_dev, 0x02 | gpp_sb_sel, 1 << 0 | 1 << 8, 1 << 0 | 1 << 8); // add bit 8 from CIMx
545 /* 4.4.2.step13.6. Set REGS_LC_ALLOW_TX_L1_CONTROL to allow TX to
546 prevent LC from going to L1 when there are outstanding completions.*/
547 set_pcie_enable_bits(dev, 0x02, 1 << 15, 1 << 15);
549 /* Enables the PLL power down when all lanes are inactive.
550 * It should be on in GPP.
552 if (gpp_sb_sel == PCIE_CORE_INDEX_GPP3a || gpp_sb_sel == PCIE_CORE_INDEX_GPP3b || gpp_sb_sel == PCIE_CORE_INDEX_SB) {
553 set_pcie_enable_bits(nb_dev, 0x02 | gpp_sb_sel, 1 << 3, 1 << 3);
556 /* 4.4.2.step13.7. Set REGS_LC_DONT_GO_TO_L0S_IF_L1_ARMED to prevent
557 lc to go to from L0 to Rcv_L0s if L1 is armed. */
558 set_pcie_enable_bits(dev, 0xA1, 1 << 11, 1 << 11);
559 /* 4.4.2.step13.8. CMGOOD_OVERRIDE for all five PCIe cores. */
560 set_nbmisc_enable_bits(nb_dev, 0x22, 1 << 27, 1 << 27);
561 /* 4.4.2.step13.9. Prevents Electrical Idle from causing a
562 transition from Rcv_L0 to Rcv_L0s. */
563 set_pcie_enable_bits(dev, 0xB1, 1 << 20, 1 << 20);
564 /* 4.4.2.step13.10. Prevents the LTSSM from going to Rcv_L0s if
565 it has already acknowledged a request to go
566 to L1 but it has not transitioned there yet. */
567 /* seems the same as step13.7 */
568 set_pcie_enable_bits(dev, 0xA1, 1 << 11, 1 << 11);
569 /* 4.4.2.step13.11. Transmits FTS before Recovery. */
570 set_pcie_enable_bits(dev, 0xA3, 1 << 9, 1 << 9);
571 /* 4.4.2.step13.12. Sets TX arbitration algorithm to round robin
572 for PCIE-GPP1, PCIE-GPP2, PCIE-GPP3a and PCIE-GPP3b cores only. */
573 //if (gpp_sb_sel != PCIE_CORE_INDEX_SB) /* RPR NOT set SB_CORE, BTS set SB_CORE, we comply with BTS */
574 set_pcie_enable_bits(nb_dev, 0x1C | gpp_sb_sel, 0x7FF, 0x109);
575 /* 4.4.2.step13.13. Sets number of TX Clocks to drain TX Pipe to 0x3.*/
576 set_pcie_enable_bits(dev, 0xA0, 0xF << 4, 0x3 << 4);
577 /* 4.4.2.step13.14. Lets PI use Electrical Idle from PHY when
578 turning off PLL in L1 at Gen 2 speed instead of Inferred Electrical
580 NOTE: LC still uses Inferred Electrical Idle. */
581 set_pcie_enable_bits(nb_dev, 0x40 | gpp_sb_sel, 3 << 14, 2 << 14);
582 /* 4.4.2.step13.15. Turn on rx_fronten_en for all active lanes upon
583 exit from Electrical Idle, rather than being tied to PLL_PDNB. */
584 set_pcie_enable_bits(nb_dev, 0xC2 | gpp_sb_sel, 1 << 25, 1 << 25);
586 /* 4.4.2.step13.16. Advertises TX L0s and L1 exit latency.
587 TX L0s exit latency to be 100b: 512ns to less than 1us;
588 L1 exit latency to be 011b: 4us to less than 8us.
589 For Hot-Plug Slots: Advertise TX L0s and L1 exit latency.
590 TX L0s exit latency to be 110b: 2us to 4us.
591 L1 exit latency to be 111b: more than 64us.*/
592 //set_pcie_enable_bits(dev, 0xC1, 0xF << 0, 0xC << 0); /* 0xF for htplg. */
593 set_pcie_enable_bits(dev, 0xC1, 0xF << 0, 0xF << 0); /* 0xF for htplg. */
594 /* 4.4.2.step13.17. Always ACK an ASPM L1 entry DLLP to
595 workaround credit control issue on PM_NAK
596 message of SB700 and SB800. */
597 /* 4.4.4.step13.18. To allow advertising Gen 2 capabilities to Southbridge. */
599 set_pcie_enable_bits(dev, 0xA0, 1 << 23, 1 << 23);
600 set_pcie_enable_bits(nb_dev, 0xC1 | gpp_sb_sel, 1 << 1, 1 << 1);
602 /* 4.4.2.step13.19. CMOS Option (Gen 2 AUTO-Part 1 - Enabled by Default) */
603 /* 4.4.2.step13.20. CMOS Option (RC Advertised Gen 2-Part1 - Disabled by Default)*/
604 set_nbcfg_enable_bits(dev, 0x88, 0xF << 0, 0x2 << 0);
605 /* Disables GEN2 capability of the device.
606 * RPR typo- it says enable but the bit setting says disable.
607 * Disable it here and we enable it later. */
608 set_pcie_enable_bits(dev, 0xA4, 1 << 0, 1 << 0);
610 /* 4.4.2.step13.21. Legacy Hot Plug -CMOS Option */
611 /* NOTE: This feature can be enabled only for Hot-Plug slots implemented on SR5690 platform. */
613 /* 4.4.2.step13.22. Native PCIe Mode -CMOS Option */
614 /* Enable native PME. */
615 set_pcie_enable_bits(dev, 0x10, 1 << 3, 1 < 3);
616 /* This bit when set indicates that the PCIe Link associated with this port
617 is connected to a slot. */
618 pci_ext_write_config32(nb_dev, dev, 0x5a, 1 << 8, 1 << 8);
619 /* This bit when set indicates that this slot is capable of supporting
620 Hot-Plug operations. */
621 set_nbcfg_enable_bits(dev, 0x6C, 1 << 6, 1 << 6);
622 /* Enables flushing of TLPs when Data Link is down. */
623 set_pcie_enable_bits(dev, 0x20, 1 << 19, 0 << 19);
625 /* 4.4.2.step14. Server Class Hot Plug Feature. NOTE: This feature is not supported on SR5670 and SR5650 */
626 /* 4.4.2 step14.1: Advertising Hot Plug Capabilities */
627 /* 4.4.2.step14.2: Firmware Upload */
628 /* 4.4.2.Step14.3: SBIOS Acknowledgment to Firmware of Successful Firmware Upload */
633 /* CIMx LPC Deadlock workaround - Enable Memory Write Map*/
634 if (gpp_sb_sel == PCIE_CORE_INDEX_SB) {
635 set_pcie_enable_bits(nb_dev, 0x10 | gpp_sb_sel, 1 << 9, 1 << 9);
636 set_htiu_enable_bits(nb_dev, 0x06, 1 << 26, 1 << 26);
639 /* This CPL setup requires more than this one register and should be done in gpp_core.
640 * The additional setup is for the different revisions. */
642 /* CIMx CommonPortInit settings that are not set above. */
643 pci_ext_write_config32(nb_dev, dev, 0x88, 0xF0, 1 << 0); /* LINK_CRTL2 */
646 set_pcie_enable_bits(dev, 0xA0, 0, 1 << 23);
648 #if 0 //SR56x0 pcie Gen2 code is not tested yet, we should enable it again when test finished.
649 /* set automatic Gen2 support, needs mainboard config option as Gen2 can cause issues on some platforms. */
650 init_gen2(nb_dev, dev, port);
651 set_pcie_enable_bits(dev, 0xA4, 1 << 29, 1 << 29);
652 set_pcie_enable_bits(dev, 0xC0, 1 << 15, 0);
653 set_pcie_enable_bits(dev, 0xA2, 1 << 13, 0);
656 /* Hotplug Support - bit5 + bit6 capable and surprise */
657 pci_ext_write_config32(nb_dev, dev, 0x6c, 0x60, 0x60);
659 /* Set interrupt pin info 0x3d */
660 pci_ext_write_config32(nb_dev, dev, 0x3c, 1 << 8, 1 << 8);
662 /* 5.12.9.3 Hotplug step 1 - NB_PCIE_ROOT_CTRL - enable pm irq
663 The RPR is wrong - this is not a PCIEND_P register */
664 pci_ext_write_config32(nb_dev, dev, 0x74, 1 << 3, 1 << 3);
666 /* 5.12.9.3 step 2 - PCIEP_PORT_CNTL - enable hotplug messages */
668 set_pcie_enable_bits(dev, 0x10, 1 << 2, 1 << 2);
670 /* Not sure about this PME setup */
672 set_pcie_enable_bits(dev, 0x10, 1 << 3, 1 << 3); /* Not set in CIMx */
675 pci_ext_write_config32(nb_dev, dev, 0x54, 1 << 8, 1 << 8); /* Not in CIMx */
677 /* 4.4.3 Training for GPP devices */
691 /* 4.4.2.step13.5. Blocks DMA traffic during C3 state */
692 set_pcie_enable_bits(dev, 0x10, 1 << 0, 0 << 0);
693 /* Enabels TLP flushing */
694 set_pcie_enable_bits(dev, 0x20, 1 << 19, 0 << 19);
696 /* check port enable */
697 if (cfg->port_enable & (1 << port)) {
698 PcieReleasePortTraining(nb_dev, dev, port);
699 if (!(AtiPcieCfg.Config & PCIE_GPP_COMPLIANCE)) {
700 u8 res = PcieTrainPort(nb_dev, dev, port);
701 printk(BIOS_DEBUG, "PcieTrainPort port=0x%x result=%d\n", port, res);
703 AtiPcieCfg.PortDetect |= 1 << port;
714 /* Re-enable RC ordering logic after training (from CIMx)*/
715 set_pcie_enable_bits(nb_dev, 0x20 | gpp_sb_sel, 1 << 9, 0);
717 /* Advertising Hot Plug Capabilities */
718 pci_ext_write_config32(nb_dev, dev, 0x6c, 0x04001B, 0x00001B);
720 /* PCIE Late Init (CIMx late init - Maybe move somewhere else? Later in the coreboot PCI device enum?) */
721 /* Set Slot Number */
722 pci_ext_write_config32(nb_dev, dev, 0x6c, 0x1FFF << 19, port << 19);
724 /* Set Slot present 0x5A*/
725 pci_ext_write_config32(nb_dev, dev, 0x58, 1 << 24, 1 << 24);
727 //PCIE-GPP1 TXCLK Clock Gating In L1 Late Core sttting - Maybe move somewhere else? */
728 set_pcie_enable_bits(nb_dev, 0x11 | gpp_sb_sel, 0xF << 0, 0x0C << 0);
729 /* Enable powering down PLLs in L1 or L23 Ready states.
730 * Turns off PHY`s RX FRONTEND during L1 when PLL power down is enabled */
731 set_pcie_enable_bits(nb_dev, 0x40 | gpp_sb_sel, 0x1219, 0x1009);
732 /* 4.4..7.1 TXCLK Gating in L1, Enables powering down TXCLK clock pads on the receive side. */
733 set_pcie_enable_bits(nb_dev, 0x40 | gpp_sb_sel, 1 << 6, 1 << 6);
735 /* Step 20: Disables immediate RCB timeout on link down */
736 if (!((pci_read_config32(dev, 0x6C ) >> 6) & 0x01)) {
737 set_pcie_enable_bits(dev, 0x70, 1 << 19, 0 << 19);
740 /* Step 27: LCLK Gating */
741 EnableLclkGating(dev);
743 /* Set Common Clock */
744 /* If dev present, set PcieCapPtr+0x10, BIT6);
746 * retrain link, set dev, 0x68 bit 5;
747 * wait dev 0x6B bit3 clear
751 PciePowerOffGppPorts(nb_dev, dev, port); /* , This should be run for all ports that are not hotplug and don't detect devices */
756 * Step 21: Register Locking
757 * Lock HWInit Register of each pcie core
759 static void lock_hwinitreg(device_t nb_dev)
761 /* Step 21: Register Locking, Lock HWInit Register */
762 set_pcie_enable_bits(nb_dev, 0x10 | PCIE_CORE_INDEX_GPP1, 1 << 0, 1 << 0);
763 set_pcie_enable_bits(nb_dev, 0x10 | PCIE_CORE_INDEX_SB, 1 << 0, 1 << 0);
764 set_pcie_enable_bits(nb_dev, 0x10 | PCIE_CORE_INDEX_GPP2, 1 << 0, 1 << 0);
765 set_pcie_enable_bits(nb_dev, 0x10 | PCIE_CORE_INDEX_GPP3a, 1 << 0, 1 << 0);
766 set_pcie_enable_bits(nb_dev, 0x10 | PCIE_CORE_INDEX_GPP3b, 1 << 0, 1 << 0);
770 * Lock HWInit Register
772 void sr56x0_lock_hwinitreg(void)
774 device_t nb_dev = dev_find_slot(0, PCI_DEVFN(0, 0));
776 /* Lock HWInit Register */
777 lock_hwinitreg(nb_dev);
779 /* Lock HWInit Register NBMISCIND:0x0 NBCNTL[7] HWINIT_WR_LOCK */
780 set_nbmisc_enable_bits(nb_dev, 0x00, 1 << 7, 1 << 7);
783 /*****************************************
784 * Compliant with CIM_33's PCIEConfigureGPPCore
785 *****************************************/
786 void config_gpp_core(device_t nb_dev, device_t sb_dev)
789 struct southbridge_amd_sr5650_config *cfg =
790 (struct southbridge_amd_sr5650_config *)nb_dev->chip_info;
792 reg = nbmisc_read_index(nb_dev, 0x20);
793 if (AtiPcieCfg.Config & PCIE_ENABLE_STATIC_DEV_REMAP)
794 reg &= 0xfffffffd; /* set bit1 = 0 */
796 reg |= 0x2; /* set bit1 = 1 */
797 nbmisc_write_index(nb_dev, 0x20, reg);
799 /* Must perform PCIE-GPP1, GPP2, GPP3a global reset anyway */
800 reg = nbmisc_read_index(nb_dev, 0x8);
801 reg |= (1 << 31) | (1 << 15) | (1 << 13); //asserts
802 nbmisc_write_index(nb_dev, 0x8, reg);
803 reg &= ~((1 << 31) | (1 << 15) | (1 << 13)); //De-aserts
804 nbmisc_write_index(nb_dev, 0x8, reg);
806 reg = nbmisc_read_index(nb_dev, 0x67); /* get STRAP_BIF_LINK_CONFIG at bit 0-4 */
807 if (cfg->gpp3a_configuration != (reg & 0x1F))
808 switching_gpp3a_configurations(nb_dev, sb_dev);
809 reg = nbmisc_read_index(nb_dev, 0x8); /* get MULTIPORT_CONFIG_GPP1 MULTIPORT_CONFIG_CONFIG_GPP2 at bit 8,9 */
810 if ((cfg->gpp1_configuration << 8) != (reg & (1 << 8)))
811 switching_gpp1_configurations(nb_dev, sb_dev);
812 if ((cfg->gpp2_configuration << 9) != (reg & (1 << 9)))
813 switching_gpp2_configurations(nb_dev, sb_dev);
814 ValidatePortEn(nb_dev);
817 /*****************************************
818 * Compliant with CIM_33's PCIEMiscClkProg
819 *****************************************/
820 void pcie_config_misc_clk(device_t nb_dev)
823 //struct bus pbus; /* fake bus for dev0 fun1 */
825 reg = pci_read_config32(nb_dev, 0x4c);
827 pci_write_config32(nb_dev, 0x4c, reg);
829 #if 0 /* TODO: Check the mics clock later. */
830 if (AtiPcieCfg.Config & PCIE_GFX_CLK_GATING) {
831 /* TXCLK Clock Gating */
832 set_nbmisc_enable_bits(nb_dev, 0x07, 3 << 0, 3 << 0);
833 set_nbmisc_enable_bits(nb_dev, 0x07, 1 << 22, 1 << 22);
834 set_pcie_enable_bits(nb_dev, 0x11 | PCIE_CORE_INDEX_GFX, (3 << 6) | (~0xf), 3 << 6);
836 /* LCLK Clock Gating */
837 reg = pci_cf8_conf1.read32(&pbus, 0, 1, 0x94);
839 pci_cf8_conf1.write32(&pbus, 0, 1, 0x94, reg);
842 if (AtiPcieCfg.Config & PCIE_GPP_CLK_GATING) {
843 /* TXCLK Clock Gating */
844 set_nbmisc_enable_bits(nb_dev, 0x07, 3 << 4, 3 << 4);
845 set_nbmisc_enable_bits(nb_dev, 0x07, 1 << 22, 1 << 22);
846 set_pcie_enable_bits(nb_dev, 0x11 | PCIE_CORE_INDEX_SB, (3 << 6) | (~0xf), 3 << 6);
848 /* LCLK Clock Gating */
849 reg = pci_cf8_conf1.read32(&pbus, 0, 1, 0x94);
851 pci_cf8_conf1.write32(&pbus, 0, 1, 0x94, reg);
855 reg = pci_read_config32(nb_dev, 0x4c);
857 pci_write_config32(nb_dev, 0x4c, reg);