2 * This file is part of the coreboot project.
4 * Copyright (C) 2010 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 #include <console/console.h>
21 #include <device/device.h>
22 #include <device/pci.h>
23 #include <device/pci_ids.h>
24 #include <device/pci_ops.h>
25 #include <device/smbus.h>
26 #include <pc80/mc146818rtc.h>
29 #include <cpu/x86/lapic.h>
30 #include <arch/ioapic.h>
33 #include "sb700_smbus.c"
37 #define MAINBOARD_POWER_OFF 0
38 #define MAINBOARD_POWER_ON 1
40 #ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
41 #define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
45 * SB700 enables all USB controllers by default in SMBUS Control.
46 * SB700 enables SATA by default in SMBUS Control.
48 static void sm_init(device_t dev)
57 printk(BIOS_INFO, "sm_init().\n");
59 ioapic_base = pci_read_config32(dev, 0x74) & (0xffffffe0); /* some like mem resource, but does not have enable bit */
60 /* Don't rename APIC ID */
61 /* TODO: We should call setup_ioapic() here. But kernel hangs if cpu is K8.
62 * We need to check out why and change back. */
63 clear_ioapic(ioapic_base);
65 /* 2.10 Interrupt Routing/Filtering */
66 dword = pci_read_config8(dev, 0x62);
68 pci_write_config8(dev, 0x62, dword);
70 /* Delay back to back interrupts to the CPU. */
71 dword = pci_read_config16(dev, 0x64);
73 pci_write_config16(dev, 0x64, dword);
75 /* rrg:K8 INTR Enable (BIOS should set this bit after PIC initialization) */
76 /* rpr 2.1 Enabling Legacy Interrupt */
77 dword = pci_read_config8(dev, 0x62);
79 pci_write_config8(dev, 0x62, dword);
81 dword = pci_read_config32(dev, 0x78);
83 pci_write_config32(dev, 0x78, dword); /* enable 0xCD6 0xCD7 */
85 /* bit 10: MultiMediaTimerIrqEn */
86 dword = pci_read_config8(dev, 0x64);
88 pci_write_config8(dev, 0x64, dword);
89 /* enable serial irq */
90 byte = pci_read_config8(dev, 0x69);
91 byte |= 1 << 7; /* enable serial irq function */
93 byte |= 4 << 2; /* set NumSerIrqBits=4 */
94 pci_write_config8(dev, 0x69, byte);
97 byte = pci_read_config8(dev, 0x41);
99 pci_write_config8(dev, 0x41, byte);
101 byte = pm_ioread(0x61);
102 byte |= 1 << 1; /* Set to enable NB/SB handshake during IOAPIC interrupt for AMD K8/K7 */
103 pm_iowrite(0x61, byte);
106 byte = pm_ioread(0x53);
108 pm_iowrite(0x53, byte);
110 /* power after power fail */
111 on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
112 get_option(&on, "power_on_after_fail");
113 byte = pm_ioread(0x74);
119 pm_iowrite(0x74, byte);
120 printk(BIOS_INFO, "set power %s after power fail\n", on ? "on" : "off");
122 byte = pm_ioread(0x68);
126 pm_iowrite(0x68, byte);
129 byte = pm_ioread(0x65);
131 pm_iowrite(0x65, byte);
134 byte = pm_ioread(0x55);
136 pm_iowrite(0x55, byte);
138 byte = pm_ioread(0xD7);
139 byte |= 1 << 6 | 1 << 1;;
140 pm_iowrite(0xD7, byte);
143 byte = pm_ioread(0x42);
145 pm_iowrite(0x42, byte);
147 /* Set up NMI on errors */
148 byte = inb(0x70); /* RTC70 */
150 nmi_option = NMI_OFF;
151 get_option(&nmi_option, "nmi");
153 byte &= ~(1 << 7); /* set NMI */
154 printk(BIOS_INFO, "++++++++++set NMI+++++\n");
156 byte |= (1 << 7); /* Can not mask NMI from PCI-E and NMI_NOW */
157 printk(BIOS_INFO, "++++++++++no set NMI+++++\n");
160 if (byte != byte_old) {
164 /* 2.11 IO Trap Settings */
165 abcfg_reg(0x10090, 1 << 16, 1 << 16);
168 pci_write_config32(dev, 0xF0, AB_INDX);
169 /* Initialize the real time clock */
172 /* 4.3 Enabling Upstream DMA Access */
173 axcfg_reg(0x04, 1 << 2, 1 << 2);
174 /* 4.4 Enabling IDE/PCIB Prefetch for Performance Enhancement */
175 abcfg_reg(0x10060, 9 << 17, 9 << 17);
176 abcfg_reg(0x10064, 9 << 17, 9 << 17);
178 /* 4.5 Enabling OHCI Prefetch for Performance Enhancement, A12 */
179 abcfg_reg(0x80, 1 << 0, 1<< 0);
181 /* 4.6 B-Link Client's Credit Variable Settings for the Downstream Arbitration Equation */
182 /* 4.7 Enabling Additional Address Bits Checking in Downstream */
183 /* 4.15 IO write and SMI ordering enhancement*/
184 abcfg_reg(0x9c, 3 << 0 | 1 << 8, 3 << 0 | 1 << 8);
186 /* 4.8 Set B-Link Prefetch Mode */
187 abcfg_reg(0x80, 3 << 17, 3 << 17);
189 /* 4.9 Enabling Detection of Upstream Interrupts */
190 abcfg_reg(0x94, 1 << 20 | 0x7FFFF, 1 << 20 | 0x00FEE);
192 /* 4.10: Enabling Downstream Posted Transactions to Pass Non-Posted
193 * Transactions for the K8 Platform (for All Revisions) */
194 abcfg_reg(0x10090, 1 << 8, 1 << 8);
196 /* 4.11:Programming Cycle Delay for AB and BIF Clock Gating */
197 /* 4.12: Enabling AB and BIF Clock Gating */
198 abcfg_reg(0x10054, 0xFFFF0000, 0x1040000);
199 abcfg_reg(0x54, 0xFF << 16, 4 << 16);
200 abcfg_reg(0x54, 1 << 24, 0 << 24);
201 abcfg_reg(0x98, 0x0000FF00, 0x00004700);
203 /* 4.13:Enabling AB Int_Arbiter Enhancement (for All Revisions) */
204 abcfg_reg(0x10054, 0x0000FFFF, 0x07FF);
206 /* 4.14:Enabling Requester ID for upstream traffic. */
207 abcfg_reg(0x98, 1 << 16, 1 << 16);
209 /* 9.2: Enabling IDE Data Bus DD7 Pull Down Resistor */
210 byte = pm2_ioread(0xE5);
212 pm2_iowrite(0xE5, byte);
214 /* Enable IDE controller. */
215 byte = pm_ioread(0x59);
217 pm_iowrite(0x59, byte);
219 printk(BIOS_INFO, "sm_init() end\n");
221 /* Enable NbSb virtual channel */
222 axcfg_reg(0x114, 0x3f << 1, 0 << 1);
223 axcfg_reg(0x120, 0x7f << 1, 0x7f << 1);
224 axcfg_reg(0x120, 7 << 24, 1 << 24);
225 axcfg_reg(0x120, 1 << 31, 1 << 31);
226 abcfg_reg(0x50, 1 << 3, 1 << 3);
229 static int lsmbus_recv_byte(device_t dev)
232 struct resource *res;
235 device = dev->path.i2c.device;
236 pbus = get_pbus_smbus(dev);
238 res = find_resource(pbus->dev, 0x90);
240 return do_smbus_recv_byte(res->base, device);
243 static int lsmbus_send_byte(device_t dev, u8 val)
246 struct resource *res;
249 device = dev->path.i2c.device;
250 pbus = get_pbus_smbus(dev);
252 res = find_resource(pbus->dev, 0x90);
254 return do_smbus_send_byte(res->base, device, val);
257 static int lsmbus_read_byte(device_t dev, u8 address)
260 struct resource *res;
263 device = dev->path.i2c.device;
264 pbus = get_pbus_smbus(dev);
266 res = find_resource(pbus->dev, 0x90);
268 return do_smbus_read_byte(res->base, device, address);
271 static int lsmbus_write_byte(device_t dev, u8 address, u8 val)
274 struct resource *res;
277 device = dev->path.i2c.device;
278 pbus = get_pbus_smbus(dev);
280 res = find_resource(pbus->dev, 0x90);
282 return do_smbus_write_byte(res->base, device, address, val);
285 static struct smbus_bus_operations lops_smbus_bus = {
286 .recv_byte = lsmbus_recv_byte,
287 .send_byte = lsmbus_send_byte,
288 .read_byte = lsmbus_read_byte,
289 .write_byte = lsmbus_write_byte,
292 static void sb700_sm_read_resources(device_t dev)
294 struct resource *res;
297 /* rpr2.14: Hides SM bus controller Bar1 where stores HPET MMIO base address */
298 byte = pm_ioread(0x55);
300 pm_iowrite(0x55, byte);
302 /* Get the normal pci resources of this device */
303 /* pci_dev_read_resources(dev); */
305 byte = pm_ioread(0x55);
307 pm_iowrite(0x55, byte);
310 res = new_resource(dev, 0x74);
311 res->base = 0xfec00000;
312 res->size = 256 * 0x10;
313 res->limit = 0xFFFFFFFFUL; /* res->base + res->size -1; */
316 res->flags = IORESOURCE_MEM | IORESOURCE_FIXED;
318 #if 0 /* Linux ACPI crashes when it is 1. For late debugging. */
319 res = new_resource(dev, 0x14); /* TODO: hpet */
320 res->base = 0xfed00000; /* reset hpet to widely accepted address */
322 res->limit = 0xFFFFFFFFUL; /* res->base + res->size -1; */
325 res->flags = IORESOURCE_MEM | IORESOURCE_FIXED;
327 /* dev->command |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; */
330 res = new_resource(dev, 0x90);
333 res->limit = 0xFFFFUL; /* res->base + res->size -1; */
336 res->flags = IORESOURCE_IO | IORESOURCE_FIXED;
338 compact_resources(dev);
341 static void sb700_sm_set_resources(struct device *dev)
343 struct resource *res;
346 pci_dev_set_resources(dev);
348 /* rpr2.14: Make HPET MMIO decoding controlled by the memory enable bit in command register of LPC ISA bridge */
349 byte = pm_ioread(0x52);
351 pm_iowrite(0x52, byte);
353 res = find_resource(dev, 0x74);
354 pci_write_config32(dev, 0x74, res->base | 1 << 3);
355 #if 0 /* TODO:hpet */
356 res = find_resource(dev, 0x14);
357 pci_write_config32(dev, 0x14, res->base);
359 res = find_resource(dev, 0x90);
360 pci_write_config32(dev, 0x90, res->base | 1);
363 static struct pci_operations lops_pci = {
364 .set_subsystem = pci_dev_set_subsystem,
367 static struct device_operations smbus_ops = {
368 .read_resources = sb700_sm_read_resources,
369 .set_resources = sb700_sm_set_resources,
370 .enable_resources = pci_dev_enable_resources,
372 .scan_bus = scan_static_bus,
373 .ops_pci = &lops_pci,
374 .ops_smbus_bus = &lops_smbus_bus,
377 static const struct pci_driver smbus_driver __pci_driver = {
379 .vendor = PCI_VENDOR_ID_ATI,
380 .device = PCI_DEVICE_ID_ATI_SB700_SM,