2 * This file is part of the coreboot project.
4 * Copyright (C) 2010 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 #include <console/console.h>
21 #include <device/device.h>
22 #include <device/pci.h>
23 #include <device/pnp.h>
24 #include <device/pci_ids.h>
25 #include <device/pci_ops.h>
26 #include <pc80/mc146818rtc.h>
27 #include <pc80/isa-dma.h>
32 static void lpc_init(device_t dev)
38 /* Enable the LPC Controller */
39 sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
40 dword = pci_read_config32(sm_dev, 0x64);
42 pci_write_config32(sm_dev, 0x64, dword);
44 /* Initialize isa dma */
47 /* Enable DMA transaction on the LPC bus */
48 byte = pci_read_config8(dev, 0x40);
50 pci_write_config8(dev, 0x40, byte);
52 /* Disable the timeout mechanism on LPC */
53 byte = pci_read_config8(dev, 0x48);
55 pci_write_config8(dev, 0x48, byte);
57 /* Disable LPC MSI Capability */
58 byte = pci_read_config8(dev, 0x78);
60 pci_write_config8(dev, 0x78, byte);
64 static void sb700_lpc_read_resources(device_t dev)
68 /* Get the normal pci resources of this device */
69 pci_dev_read_resources(dev); /* We got one for APIC, or one more for TRAP */
71 pci_get_resource(dev, 0xA0); /* SPI ROM base address */
73 /* Add an extra subtractive resource for both memory and I/O. */
74 res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
77 res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
78 IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
80 res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
81 res->base = 0xff800000;
82 res->size = 0x00800000; /* 8 MB for flash */
83 res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
84 IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
86 res = new_resource(dev, 3); /* IOAPIC */
87 res->base = 0xfec00000;
88 res->size = 0x00001000;
89 res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
91 compact_resources(dev);
94 static void sb700_lpc_set_resources(struct device *dev)
99 pci_dev_set_resources(dev);
101 /* Specical case. SPI Base Address. The SpiRomEnable should be set. */
102 res = find_resource(dev, 0xA0);
103 pci_write_config32(dev, 0xA0, res->base | 1 << 1);
108 * @brief Enable resources for children devices
110 * @param dev the device whos children's resources are to be enabled
112 * This function is call by the global enable_resources() indirectly via the
113 * device_operation::enable_resources() method of devices.
115 * Indirect mutual recursion:
116 * enable_childrens_resources() -> enable_resources()
117 * enable_resources() -> device_operation::enable_resources()
118 * device_operation::enable_resources() -> enable_children_resources()
120 static void sb700_lpc_enable_childrens_resources(device_t dev)
128 reg = pci_read_config32(dev, 0x44);
129 reg_x = pci_read_config32(dev, 0x48);
131 for (link = 0; link < dev->links; link++) {
133 for (child = dev->link[link].children; child;
134 child = child->sibling) {
135 enable_resources(child);
137 && (child->path.type == DEVICE_PATH_PNP)) {
138 for (i = 0; i < child->resources; i++) {
139 struct resource *res;
140 u32 base, end; /* don't need long long */
141 res = &child->resource[i];
142 if (!(res->flags & IORESOURCE_IO))
145 end = resource_end(res);
147 ("sb700 lpc decode:%s, base=0x%08x, end=0x%08x\n",
148 dev_path(child), base, end);
154 case 0x3f8: /* COM1 */
157 case 0x2f8: /* COM2 */
160 case 0x378: /* Parallal 1 */
163 case 0x3f0: /* FD0 */
166 case 0x220: /* Aduio 0 */
169 case 0x300: /* Midi 0 */
192 continue; /* only 3 var ; compact them ? */
211 pci_write_config32(dev, 0x44, reg);
212 pci_write_config32(dev, 0x48, reg_x);
213 /* Set WideIO for as many IOs found (fall through is on purpose) */
216 pci_write_config16(dev, 0x90, reg_var[2]);
218 pci_write_config16(dev, 0x66, reg_var[1]);
220 pci_write_config16(dev, 0x64, reg_var[0]);
225 static void sb700_lpc_enable_resources(device_t dev)
227 pci_dev_enable_resources(dev);
228 sb700_lpc_enable_childrens_resources(dev);
231 static struct pci_operations lops_pci = {
232 .set_subsystem = pci_dev_set_subsystem,
235 static struct device_operations lpc_ops = {
236 .read_resources = sb700_lpc_read_resources,
237 .set_resources = sb700_lpc_set_resources,
238 .enable_resources = sb700_lpc_enable_resources,
240 .scan_bus = scan_static_bus,
241 .ops_pci = &lops_pci,
243 static const struct pci_driver lpc_driver __pci_driver = {
245 .vendor = PCI_VENDOR_ID_ATI,
246 .device = PCI_DEVICE_ID_ATI_SB700_LPC,