2 * This file is part of the coreboot project.
4 * Copyright (C) 2010 Advanced Micro Devices, Inc.
5 * Copyright (C) 2010 Uwe Hermann <uwe@hermann-uwe.de>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
23 #include <arch/romcc_io.h>
25 #include <device/pci_def.h>
28 #define EHCI_EOR (CONFIG_EHCI_BAR + 0x20)
29 #define DEBUGPORT_MISC_CONTROL (EHCI_EOR + 0x80)
31 void set_debug_port(unsigned int port)
35 /* Write the port number to DEBUGPORT_MISC_CONTROL[31:28]. */
36 reg32 = read32(DEBUGPORT_MISC_CONTROL);
37 reg32 &= ~(0xf << 28);
38 reg32 |= (port << 28);
39 reg32 |= (1 << 27); /* Enable Debug Port port number remapping. */
40 write32(DEBUGPORT_MISC_CONTROL, reg32);
44 * Note: The SB700 has two EHCI devices, D18:F2 and D19:F2.
45 * This code currently only supports the first one, i.e., USB Debug devices
46 * attached to physical USB ports belonging to the first EHCI device.
48 void sb700_enable_usbdebug(unsigned int port)
50 device_t dev = PCI_DEV(0, 0x12, 2); /* USB EHCI, D18:F2 */
52 /* Set the EHCI BAR address. */
53 pci_write_config32(dev, EHCI_BAR_INDEX, CONFIG_EHCI_BAR);
55 /* Enable access to the EHCI memory space registers. */
56 pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);
59 * Select the requested physical USB port (1-15) as the Debug Port.
60 * Must be called after the EHCI BAR has been set up (see above).