2 * This file is part of the coreboot project.
4 * Copyright (C) 2008 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 #include <console/console.h>
21 #include <device/device.h>
22 #include <device/pci.h>
23 #include <device/pci_ids.h>
24 #include <device/pci_ops.h>
25 #include <device/smbus.h>
26 #include <pc80/mc146818rtc.h>
29 #include <cpu/x86/lapic.h>
30 #include <arch/ioapic.h>
37 #define MAINBOARD_POWER_OFF 0
38 #define MAINBOARD_POWER_ON 1
40 #ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
41 #define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
45 * SB600 enables all USB controllers by default in SMBUS Control.
46 * SB600 enables SATA by default in SMBUS Control.
48 static void sm_init(device_t dev)
57 printk(BIOS_INFO, "sm_init().\n");
59 ioapic_base = pci_read_config32(dev, 0x74) & (0xffffffe0); /* some like mem resource, but does not have enable bit */
60 /* Don't rename APIC ID */
61 clear_ioapic(ioapic_base);
63 dword = pci_read_config8(dev, 0x62);
65 pci_write_config8(dev, 0x62, dword);
67 dword = pci_read_config32(dev, 0x78);
69 pci_write_config32(dev, 0x78, dword); /* enable 0xCD6 0xCD7 */
71 /* bit 10: MultiMediaTimerIrqEn */
72 dword = pci_read_config8(dev, 0x64);
74 pci_write_config8(dev, 0x64, dword);
75 /* enable serial irq */
76 byte = pci_read_config8(dev, 0x69);
77 byte |= 1 << 7; /* enable serial irq function */
79 byte |= 4 << 2; /* set NumSerIrqBits=4 */
80 pci_write_config8(dev, 0x69, byte);
82 byte = pm_ioread(0x61);
83 byte |= 1 << 1; /* Set to enable NB/SB handshake during IOAPIC interrupt for AMD K8/K7 */
84 pm_iowrite(0x61, byte);
87 byte = pm_ioread(0x53);
89 pm_iowrite(0x53, byte);
91 /* power after power fail */
92 on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
93 get_option(&on, "power_on_after_fail");
94 byte = pm_ioread(0x74);
100 pm_iowrite(0x74, byte);
101 printk(BIOS_INFO, "set power %s after power fail\n", on ? "on" : "off");
103 /* sb600 rpr:2.3.3: */
104 byte = pm_ioread(0x9A);
105 byte |= 1 << 5 | 1 << 4 | 1 << 2;
106 pm_iowrite(0x9A, byte);
108 byte = pm_ioread(0x8F);
111 pm_iowrite(0x8F, byte);
113 pm_iowrite(0x8B, 0x01);
114 pm_iowrite(0x8A, 0x90);
115 pm_iowrite(0x88, 0x10); /* A21 */
117 byte = pm_ioread(0x7C);
119 pm_iowrite(0x7C, byte);
121 byte = pm_ioread(0x68);
125 pm_iowrite(0x68, byte);
128 byte = pm_ioread(0x65);
130 pm_iowrite(0x65, byte);
133 byte = pm_ioread(0x52);
136 pm_iowrite(0x52, byte);
138 byte = pm_ioread(0x8D);
140 pm_iowrite(0x8D, byte);
142 byte = pm_ioread(0x61);
144 pm_iowrite(0x61, byte);
146 byte = pm_ioread(0x42);
148 pm_iowrite(0x42, byte);
150 /* Set up NMI on errors */
151 byte = inb(0x70); /* RTC70 */
153 nmi_option = NMI_OFF;
154 get_option(&nmi_option, "nmi");
156 byte &= ~(1 << 7); /* set NMI */
157 printk(BIOS_INFO, "++++++++++set NMI+++++\n");
159 byte |= (1 << 7); /* Can not mask NMI from PCI-E and NMI_NOW */
160 printk(BIOS_INFO, "++++++++++no set NMI+++++\n");
163 if (byte != byte_old) {
167 /* 2.10 IO Trap Settings */
168 abcfg_reg(0x10090, 1 << 16, 1 << 16);
171 pci_write_config32(dev, 0xF0, AB_INDX);
172 /* Initialize the real time clock */
175 /*3.4 Enabling IDE/PCIB Prefetch for Performance Enhancement */
176 abcfg_reg(0x10060, 9 << 17, 9 << 17);
177 abcfg_reg(0x10064, 9 << 17, 9 << 17);
179 /* 3.5 Enabling OHCI Prefetch for Performance Enhancement */
180 abcfg_reg(0x80, 1 << 0, 1<< 0);
182 /* 3.6 B-Link Client's Credit Variable Settings for the Downstream Arbitration Equation */
183 /* 3.7 Enabling Additional Address Bits Checking in Downstream */
184 abcfg_reg(0x9c, 3 << 0, 3 << 0);
186 /* 3.8 Set B-Link Prefetch Mode */
187 abcfg_reg(0x80, 3 << 17, 3 << 17);
189 /* 3.9 Enabling Detection of Upstream Interrupts */
190 abcfg_reg(0x94, 1 << 20,1 << 20);
192 /* 3.10: Enabling Downstream Posted Transactions to Pass Non-Posted
193 * Transactions for the K8 Platform (for All Revisions) */
194 abcfg_reg(0x10090, 1 << 8, 1 << 8);
196 /* 3.11:Programming Cycle Delay for AB and BIF Clock Gating */
197 /* 3.12: Enabling AB and BIF Clock Gating */
198 abcfg_reg(0x10054, 0xFFFF0000, 0x1040000);
199 abcfg_reg(0x54, 0xFF << 16, 4 << 16);
200 printk(BIOS_INFO, "3.11, ABCFG:0x54\n");
201 abcfg_reg(0x54, 1 << 24, 1 << 24);
202 printk(BIOS_INFO, "3.12, ABCFG:0x54\n");
203 abcfg_reg(0x98, 0x0000FF00, 0x00004700);
205 /* 3.13:Enabling AB Int_Arbiter Enhancement (for All Revisions) */
206 abcfg_reg(0x10054, 0x0000FFFF, 0x07FF);
208 /* 3.14:Enabling L1 on A-link Express */
209 axcfg_reg(0x68, 0x00000003, 0x2);
210 axindxp_reg(0xa0, 0x0000F000, 0x6000);
212 abcfg_reg(0x10098, 0xFFFFFFFF, 0x4000);
213 abcfg_reg(0x04, 0xFFFFFFFF, 0x6);
214 printk(BIOS_INFO, "sm_init() end\n");
216 /* Enable NbSb virtual channel */
217 axcfg_reg(0x114, 0x3f << 1, 0 << 1);
218 axcfg_reg(0x120, 0x7f << 1, 0x7f << 1);
219 axcfg_reg(0x120, 7 << 24, 1 << 24);
220 axcfg_reg(0x120, 1 << 31, 1 << 31);
221 abcfg_reg(0x50, 1 << 3, 1 << 3);
224 static int lsmbus_recv_byte(device_t dev)
227 struct resource *res;
230 device = dev->path.i2c.device;
231 pbus = get_pbus_smbus(dev);
233 res = find_resource(pbus->dev, 0x10);
235 return do_smbus_recv_byte(res->base, device);
238 static int lsmbus_send_byte(device_t dev, u8 val)
241 struct resource *res;
244 device = dev->path.i2c.device;
245 pbus = get_pbus_smbus(dev);
247 res = find_resource(pbus->dev, 0x10);
249 return do_smbus_send_byte(res->base, device, val);
252 static int lsmbus_read_byte(device_t dev, u8 address)
255 struct resource *res;
258 device = dev->path.i2c.device;
259 pbus = get_pbus_smbus(dev);
261 res = find_resource(pbus->dev, 0x10);
263 return do_smbus_read_byte(res->base, device, address);
266 static int lsmbus_write_byte(device_t dev, u8 address, u8 val)
269 struct resource *res;
272 device = dev->path.i2c.device;
273 pbus = get_pbus_smbus(dev);
275 res = find_resource(pbus->dev, 0x10);
277 return do_smbus_write_byte(res->base, device, address, val);
279 static struct smbus_bus_operations lops_smbus_bus = {
280 .recv_byte = lsmbus_recv_byte,
281 .send_byte = lsmbus_send_byte,
282 .read_byte = lsmbus_read_byte,
283 .write_byte = lsmbus_write_byte,
286 static void sb600_sm_read_resources(device_t dev)
288 struct resource *res;
291 /* rpr2.14: Hides SM bus controller Bar1 where stores HPET MMIO base address */
292 byte = pm_ioread(0x55);
294 pm_iowrite(0x55, byte);
296 /* Get the normal pci resources of this device */
297 /* pci_dev_read_resources(dev); */
299 byte = pm_ioread(0x55);
301 pm_iowrite(0x55, byte);
304 res = new_resource(dev, 0x74);
305 res->base = IO_APIC_ADDR;
306 res->size = 256 * 0x10;
307 res->limit = 0xFFFFFFFFUL; /* res->base + res->size -1; */
310 res->flags = IORESOURCE_MEM | IORESOURCE_FIXED;
312 res = new_resource(dev, 0x14); /* hpet */
313 res->base = 0xfed00000; /* reset hpet to widely accepted address */
315 res->limit = 0xFFFFFFFFUL; /* res->base + res->size -1; */
318 res->flags = IORESOURCE_MEM | IORESOURCE_FIXED;
319 /* dev->command |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; */
322 res = new_resource(dev, 0x10);
325 res->limit = 0xFFFFUL; /* res->base + res->size -1; */
328 res->flags = IORESOURCE_IO | IORESOURCE_FIXED;
330 compact_resources(dev);
334 static void sb600_sm_set_resources(struct device *dev)
336 struct resource *res;
339 pci_dev_set_resources(dev);
341 /* rpr2.14: Make HPET MMIO decoding controlled by the memory enable bit in command register of LPC ISA bridge */
342 byte = pm_ioread(0x52);
344 pm_iowrite(0x52, byte);
346 res = find_resource(dev, 0x74);
347 pci_write_config32(dev, 0x74, res->base | 1 << 3);
349 res = find_resource(dev, 0x14);
350 pci_write_config32(dev, 0x14, res->base);
352 res = find_resource(dev, 0x10);
353 pci_write_config32(dev, 0x10, res->base | 1);
356 static struct pci_operations lops_pci = {
357 .set_subsystem = pci_dev_set_subsystem,
360 static struct device_operations smbus_ops = {
361 .read_resources = sb600_sm_read_resources,
362 .set_resources = sb600_sm_set_resources,
363 .enable_resources = pci_dev_enable_resources,
365 .scan_bus = scan_static_bus,
366 /* .enable = sb600_enable, */
367 .ops_pci = &lops_pci,
368 .ops_smbus_bus = &lops_smbus_bus,
371 static const struct pci_driver smbus_driver __pci_driver = {
373 .vendor = PCI_VENDOR_ID_ATI,
374 .device = PCI_DEVICE_ID_ATI_SB600_SM,