2 * This file is part of the coreboot project.
4 * Copyright (C) 2008 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 #include <console/console.h>
21 #include <device/device.h>
22 #include <device/pci.h>
23 #include <device/pci_ids.h>
24 #include <device/pci_ops.h>
25 #include <device/smbus.h>
26 #include <pc80/mc146818rtc.h>
29 #include <cpu/x86/lapic.h>
32 #include "sb600_smbus.c"
36 #define MAINBOARD_POWER_OFF 0
37 #define MAINBOARD_POWER_ON 1
39 #ifndef MAINBOARD_POWER_ON_AFTER_POWER_FAIL
40 #define MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
45 u32 value_low, value_high;
48 static struct ioapicreg ioapicregvalues[] = {
49 #define ALL (0xff << 24)
51 #define DISABLED (1 << 16)
52 #define ENABLED (0 << 16)
53 #define TRIGGER_EDGE (0 << 15)
54 #define TRIGGER_LEVEL (1 << 15)
55 #define POLARITY_HIGH (0 << 13)
56 #define POLARITY_LOW (1 << 13)
57 #define PHYSICAL_DEST (0 << 11)
58 #define LOGICAL_DEST (1 << 11)
59 #define ExtINT (7 << 8)
63 /* IO-APIC virtual wire mode configuration */
64 /* mask, trigger, polarity, destination, delivery, vector */
89 /* Be careful and don't write past the end... */
92 static void setup_ioapic(u32 ioapic_base)
95 u32 value_low, value_high;
97 struct ioapicreg *a = ioapicregvalues;
99 ioapicregvalues[0].value_high = lapicid() << (56 - 32);
101 printk_debug("lapicid = %016x\n", ioapicregvalues[0].value_high);
103 l = (u32 *)ioapic_base;
105 for (i = 0; i < ARRAY_SIZE(ioapicregvalues);
107 l[0] = (a->reg * 2) + 0x10;
110 l[0] = (a->reg * 2) + 0x11;
111 l[4] = a->value_high;
113 if ((i == 0) && (value_low == 0xffffffff)) {
114 printk_warning("IO APIC not responding.\n");
121 * SB600 enables all USB controllers by default in SMBUS Control.
122 * SB600 enables SATA by default in SMBUS Control.
124 static void sm_init(device_t dev)
133 printk_info("sm_init().\n");
135 ioapic_base = pci_read_config32(dev, 0x74) & (0xffffffe0); /* some like mem resource, but does not have enable bit */
136 setup_ioapic(ioapic_base);
138 dword = pci_read_config8(dev, 0x62);
140 pci_write_config8(dev, 0x62, dword);
142 dword = pci_read_config32(dev, 0x78);
144 pci_write_config32(dev, 0x78, dword); /* enable 0xCD6 0xCD7 */
146 /* bit 10: MultiMediaTimerIrqEn */
147 dword = pci_read_config8(dev, 0x64);
149 pci_write_config8(dev, 0x64, dword);
150 /* enable serial irq */
151 byte = pci_read_config8(dev, 0x69);
152 byte |= 1 << 7; /* enable serial irq function */
154 byte |= 4 << 2; /* set NumSerIrqBits=4 */
155 pci_write_config8(dev, 0x69, byte);
157 byte = pm_ioread(0x61);
158 byte |= 1 << 1; /* Set to enable NB/SB handshake during IOAPIC interrupt for AMD K8/K7 */
159 pm_iowrite(0x61, byte);
162 byte = pm_ioread(0x53);
164 pm_iowrite(0x53, byte);
166 /* power after power fail */
167 on = MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
168 get_option(&on, "power_on_after_fail");
169 byte = pm_ioread(0x74);
175 pm_iowrite(0x74, byte);
176 printk_info("set power %s after power fail\n", on ? "on" : "off");
178 /* sb600 rpr:2.3.3: */
179 byte = pm_ioread(0x9A);
180 byte |= 1 << 5 | 1 << 4 | 1 << 2;
181 pm_iowrite(0x9A, byte);
183 byte = pm_ioread(0x8F);
186 pm_iowrite(0x8F, byte);
188 pm_iowrite(0x8B, 0x01);
189 pm_iowrite(0x8A, 0x90);
190 pm_iowrite(0x88, 0x10); /* A21 */
192 byte = pm_ioread(0x7C);
194 pm_iowrite(0x7C, byte);
196 byte = pm_ioread(0x68);
200 pm_iowrite(0x68, byte);
203 byte = pm_ioread(0x65);
205 pm_iowrite(0x65, byte);
208 byte = pm_ioread(0x52);
211 pm_iowrite(0x52, byte);
213 byte = pm_ioread(0x8D);
215 pm_iowrite(0x8D, byte);
217 byte = pm_ioread(0x61);
219 pm_iowrite(0x61, byte);
221 byte = pm_ioread(0x42);
223 pm_iowrite(0x42, byte);
225 /* Set up NMI on errors */
226 byte = inb(0x70); /* RTC70 */
228 nmi_option = NMI_OFF;
229 get_option(&nmi_option, "nmi");
231 byte &= ~(1 << 7); /* set NMI */
232 printk_info("++++++++++set NMI+++++\n");
234 byte |= (1 << 7); /* Can not mask NMI from PCI-E and NMI_NOW */
235 printk_info("++++++++++no set NMI+++++\n");
238 if (byte != byte_old) {
242 /* 2.10 IO Trap Settings */
243 abcfg_reg(0x10090, 1 << 16, 1 << 16);
246 pci_write_config32(dev, 0xF0, AB_INDX);
247 /* Initialize the real time clock */
250 /*3.4 Enabling IDE/PCIB Prefetch for Performance Enhancement */
251 abcfg_reg(0x10060, 9 << 17, 9 << 17);
252 abcfg_reg(0x10064, 9 << 17, 9 << 17);
254 /* 3.5 Enabling OHCI Prefetch for Performance Enhancement */
255 abcfg_reg(0x80, 1 << 0, 1<< 0);
257 /* 3.6 B-Link Client's Credit Variable Settings for the Downstream Arbitration Equation */
258 /* 3.7 Enabling Additional Address Bits Checking in Downstream */
259 abcfg_reg(0x9c, 3 << 0, 3 << 0);
261 /* 3.8 Set B-Link Prefetch Mode */
262 abcfg_reg(0x80, 3 << 17, 3 << 17);
264 /* 3.9 Enabling Detection of Upstream Interrupts */
265 abcfg_reg(0x94, 1 << 20,1 << 20);
267 /* 3.10: Enabling Downstream Posted Transactions to Pass Non-Posted
268 * Transactions for the K8 Platform (for All Revisions) */
269 abcfg_reg(0x10090, 1 << 8, 1 << 8);
271 /* 3.11:Programming Cycle Delay for AB and BIF Clock Gating */
272 /* 3.12: Enabling AB and BIF Clock Gating */
273 abcfg_reg(0x10054, 0xFFFF0000, 0x1040000);
274 abcfg_reg(0x54, 0xFF << 16, 4 << 16);
275 printk_info("3.11, ABCFG:0x54\n");
276 abcfg_reg(0x54, 1 << 24, 1 << 24);
277 printk_info("3.12, ABCFG:0x54\n");
278 abcfg_reg(0x98, 0x0000FF00, 0x00004700);
280 /* 3.13:Enabling AB Int_Arbiter Enhancement (for All Revisions) */
281 abcfg_reg(0x10054, 0x0000FFFF, 0x07FF);
283 /* 3.14:Enabling L1 on A-link Express */
284 axcfg_reg(0x68, 0x00000003, 0x2);
285 axindxp_reg(0xa0, 0x0000F000, 0x6000);
287 abcfg_reg(0x10098, 0xFFFFFFFF, 0x4000);
288 abcfg_reg(0x04, 0xFFFFFFFF, 0x6);
289 printk_info("sm_init() end\n");
291 /* Enable NbSb virtual channel */
292 axcfg_reg(0x114, 0x3f << 1, 0 << 1);
293 axcfg_reg(0x120, 0x7f << 1, 0x7f << 1);
294 axcfg_reg(0x120, 7 << 24, 1 << 24);
295 axcfg_reg(0x120, 1 << 31, 1 << 31);
296 abcfg_reg(0x50, 1 << 3, 1 << 3);
299 static int lsmbus_recv_byte(device_t dev)
302 struct resource *res;
305 device = dev->path.i2c.device;
306 pbus = get_pbus_smbus(dev);
308 res = find_resource(pbus->dev, 0x10);
310 return do_smbus_recv_byte(res->base, device);
313 static int lsmbus_send_byte(device_t dev, u8 val)
316 struct resource *res;
319 device = dev->path.i2c.device;
320 pbus = get_pbus_smbus(dev);
322 res = find_resource(pbus->dev, 0x10);
324 return do_smbus_send_byte(res->base, device, val);
327 static int lsmbus_read_byte(device_t dev, u8 address)
330 struct resource *res;
333 device = dev->path.i2c.device;
334 pbus = get_pbus_smbus(dev);
336 res = find_resource(pbus->dev, 0x10);
338 return do_smbus_read_byte(res->base, device, address);
341 static int lsmbus_write_byte(device_t dev, u8 address, u8 val)
344 struct resource *res;
347 device = dev->path.i2c.device;
348 pbus = get_pbus_smbus(dev);
350 res = find_resource(pbus->dev, 0x10);
352 return do_smbus_write_byte(res->base, device, address, val);
354 static struct smbus_bus_operations lops_smbus_bus = {
355 .recv_byte = lsmbus_recv_byte,
356 .send_byte = lsmbus_send_byte,
357 .read_byte = lsmbus_read_byte,
358 .write_byte = lsmbus_write_byte,
361 static void sb600_sm_read_resources(device_t dev)
363 struct resource *res;
366 /* rpr2.14: Hides SM bus controller Bar1 where stores HPET MMIO base address */
367 byte = pm_ioread(0x55);
369 pm_iowrite(0x55, byte);
371 /* Get the normal pci resources of this device */
372 /* pci_dev_read_resources(dev); */
374 byte = pm_ioread(0x55);
376 pm_iowrite(0x55, byte);
379 res = new_resource(dev, 0x74);
380 res->base = 0xfec00000;
381 res->size = 256 * 0x10;
382 res->limit = 0xFFFFFFFFUL; /* res->base + res->size -1; */
385 res->flags = IORESOURCE_MEM | IORESOURCE_FIXED;
387 res = new_resource(dev, 0x14); /* hpet */
388 res->base = 0xfed00000; /* reset hpet to widely accepted address */
390 res->limit = 0xFFFFFFFFUL; /* res->base + res->size -1; */
393 res->flags = IORESOURCE_MEM | IORESOURCE_FIXED;
394 /* dev->command |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; */
397 res = new_resource(dev, 0x10);
400 res->limit = 0xFFFFUL; /* res->base + res->size -1; */
403 res->flags = IORESOURCE_IO | IORESOURCE_FIXED;
406 compact_resources(dev);
409 static void sb600_sm_set_resources(struct device *dev)
411 struct resource *res;
414 pci_dev_set_resources(dev);
417 /* rpr2.14: Make HPET MMIO decoding controlled by the memory enable bit in command register of LPC ISA bridage */
418 byte = pm_ioread(0x52);
420 pm_iowrite(0x52, byte);
422 res = find_resource(dev, 0x74);
423 pci_write_config32(dev, 0x74, res->base | 1 << 3);
425 res = find_resource(dev, 0x14);
426 pci_write_config32(dev, 0x14, res->base);
428 res = find_resource(dev, 0x10);
429 pci_write_config32(dev, 0x10, res->base | 1);
432 static struct pci_operations lops_pci = {
433 .set_subsystem = pci_dev_set_subsystem,
435 static struct device_operations smbus_ops = {
436 .read_resources = sb600_sm_read_resources,
437 .set_resources = sb600_sm_set_resources,
438 .enable_resources = pci_dev_enable_resources,
440 .scan_bus = scan_static_bus,
441 /* .enable = sb600_enable, */
442 .ops_pci = &lops_pci,
443 .ops_smbus_bus = &lops_smbus_bus,
445 static struct pci_driver smbus_driver __pci_driver = {
447 .vendor = PCI_VENDOR_ID_ATI,
448 .device = PCI_DEVICE_ID_ATI_SB600_SM,