2 * This file is part of the coreboot project.
4 * Copyright (C) 2008 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 #define PCI_DEV(BUS, DEV, FN) ( \
23 (((BUS) & 0xFFF) << 20) | \
24 (((DEV) & 0x1F) << 15) | \
29 static void pci_write_config8(device_t dev, unsigned where, unsigned char value)
32 addr = (dev>>4) | where;
33 outl(0x80000000 | (addr & ~3), 0xCF8);
34 outb(value, 0xCFC + (addr & 3));
37 static void pci_write_config32(device_t dev, unsigned where, unsigned value)
40 addr = (dev>>4) | where;
41 outl(0x80000000 | (addr & ~3), 0xCF8);
45 static unsigned pci_read_config32(device_t dev, unsigned where)
48 addr = (dev>>4) | where;
49 outl(0x80000000 | (addr & ~3), 0xCF8);
53 #include "../../../northbridge/amd/amdk8/reset_test.c"
58 /* Try rebooting through port 0xcf9 */
59 /* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */
60 outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9);
61 outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9);