2 * This file is part of the coreboot project.
4 * Copyright (C) 2008 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
23 #include "sb600_smbus.c"
25 #define SMBUS_IO_BASE 0x1000 /* Is it a temporary SMBus I/O base address? */
29 static void pmio_write(u8 reg, u8 value)
32 outb(value, PM_INDEX + 1);
35 static u8 pmio_read(u8 reg)
38 return inb(PM_INDEX + 1);
41 /* Get SB ASIC Revision.*/
42 static u8 get_sb600_revision(void)
45 dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0);
47 if (dev == PCI_DEV_INVALID) {
48 die("SMBUS controller not found\n");
51 return pci_read_config8(dev, 0x08);
55 /***************************************
56 * Legacy devices are mapped to LPC space.
59 * ACPI Micro-controller port
61 * This function does not change port 0x80 decoding.
62 * Console output through any port besides 0x3f8 is unsupported.
63 * If you use FWH ROMs, you have to setup IDSEL.
64 * NOTE: Call me ASAP, because I will reset LPC ROM size!
65 * Reviewed-by: Carl-Daniel Hailfinger
66 * Reviewed against AMD SB600 Register Reference Manual rev. 3.03, section 3.1
68 ***************************************/
69 static void sb600_lpc_init(void)
75 dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0); /* SMBUS controller */
76 /* NOTE: Set BootTimerDisable, otherwise it would keep rebooting!!
77 * This bit has no meaning if debug strap is not enabled. So if the
78 * board keeps rebooting and the code fails to reach here, we could
79 * disable the debug strap first. */
80 reg32 = pci_read_config32(dev, 0x4C);
82 pci_write_config32(dev, 0x4C, reg32);
84 /* Enable lpc controller */
85 reg32 = pci_read_config32(dev, 0x64);
87 pci_write_config32(dev, 0x64, reg32);
89 dev = pci_locate_device(PCI_ID(0x1002, 0x438d), 0); /* LPC Controller */
90 /* Decode port 0x3f8-0x3ff (Serial 0) */
91 #warning Serial port decode on LPC is hardcoded to 0x3f8
92 reg8 = pci_read_config8(dev, 0x44);
94 pci_write_config8(dev, 0x44, reg8);
96 /* Decode port 0x60 & 0x64 (PS/2 keyboard) and port 0x62 & 0x66 (ACPI)*/
97 reg8 = pci_read_config8(dev, 0x47);
98 reg8 |= (1 << 5) | (1 << 6);
99 pci_write_config8(dev, 0x47, reg8);
101 /* SuperIO, LPC ROM */
102 reg8 = pci_read_config8(dev, 0x48);
103 /* Decode ports 0x2e-0x2f, 0x4e-0x4f (SuperI/O configuration) */
104 reg8 |= (1 << 1) | (1 << 0);
105 /* Decode variable LPC ROM address ranges 1&2 (see register 0x68-0x6b, 0x6c-0x6f) */
106 reg8 |= (1 << 3) | (1 << 4);
107 /* Decode port 0x70-0x73 (RTC) */
109 pci_write_config8(dev, 0x48, reg8);
111 /* hardware should enable LPC ROM by pin straps */
112 /* ROM access at 0xFFF80000/0xFFF00000 - 0xFFFFFFFF */
113 /* See detail in BDG-215SB600-03.pdf page 15. */
114 /* enable LPC ROM range mirroring start 0x000e(0000) */
115 pci_write_config16(dev, 0x68, 0x000e);
116 /* enable LPC ROM range mirroring end 0x000f(ffff) */
117 pci_write_config16(dev, 0x6a, 0x000f);
118 /* enable LPC ROM range start, 0xfff8(0000): 512KB, 0xfff0(0000): 1MB, 0xffe0(0000): 2MB, 0xffc0(0000): 4MB */
119 pci_write_config16(dev, 0x6c, 0xffc0);
120 /* enable LPC ROM range end at 0xffff(ffff) */
121 pci_write_config16(dev, 0x6e, 0xffff);
124 /* what is its usage? */
125 static u32 get_sbdn(u32 bus)
129 /* Find the device. */
130 dev = pci_locate_device_on_bus(PCI_ID(0x1002, 0x4385), bus);
131 return (dev >> 15) & 0x1f;
135 static u8 dual_core(void)
137 return (pci_read_config32(PCI_DEV(0, 0x18, 3), 0xE8) & (0x3<<12)) != 0;
141 SB600 VFSMAF (VID/FID System Management Action Field) is 010b by default.
142 RPR 2.3.3 C-state and VID/FID change for the K8 platform.
144 static void enable_fid_change_on_sb(u32 sbbusn, u32 sbdn)
147 byte = pmio_read(0x9a);
153 pmio_write(0x9a, byte);
155 byte = pmio_read(0x8f);
158 pmio_write(0x8f, byte);
160 pmio_write(0x8b, 0x01);
161 pmio_write(0x8a, 0x90);
163 if(get_sb600_revision() > 0x13)
164 pmio_write(0x88, 0x10);
166 pmio_write(0x88, 0x06);
168 byte = pmio_read(0x7c);
171 pmio_write(0x7c, byte);
173 /*Must be 0 for K8 platform.*/
174 byte = pmio_read(0x68);
176 pmio_write(0x68, byte);
177 /*Must be 0 for K8 platform.*/
178 byte = pmio_read(0x8d);
180 pmio_write(0x8d, byte);
182 byte = pmio_read(0x61);
184 pmio_write(0x61, byte);
186 byte = pmio_read(0x42);
188 pmio_write(0x42, byte);
190 if(get_sb600_revision() == 0x14) {
191 pmio_write(0x89, 0x10);
193 byte = pmio_read(0x52);
195 pmio_write(0x52, byte);
200 void hard_reset(void)
209 void soft_reset(void)
216 static void sb600_pci_port80(void)
222 dev = pci_locate_device(PCI_ID(0x1002, 0x4384), 0);
224 /* Chip Control: Enable subtractive decoding */
225 byte = pci_read_config8(dev, 0x40);
227 pci_write_config8(dev, 0x40, byte);
229 /* Misc Control: Enable subtractive decoding if 0x40 bit 5 is set */
230 byte = pci_read_config8(dev, 0x4B);
232 pci_write_config8(dev, 0x4B, byte);
234 /* The same IO Base and IO Limit here is meaningful because we set the
235 * bridge to be subtractive. During early setup stage, we have to make
236 * sure that data can go through port 0x80.
238 /* IO Base: 0xf000 */
239 byte = pci_read_config8(dev, 0x1C);
241 pci_write_config8(dev, 0x1C, byte);
243 /* IO Limit: 0xf000 */
244 byte = pci_read_config8(dev, 0x1D);
246 pci_write_config8(dev, 0x1D, byte);
248 /* PCI Command: Enable IO response */
249 byte = pci_read_config8(dev, 0x04);
251 pci_write_config8(dev, 0x04, byte);
254 dev = pci_locate_device(PCI_ID(0x1002, 0x438D), 0);
256 byte = pci_read_config8(dev, 0x4A);
257 byte &= ~(1 << 5); /* disable lpc port 80 */
258 pci_write_config8(dev, 0x4A, byte);
261 static void sb600_lpc_port80(void)
267 /* Enable LPC controller */
268 dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0);
269 reg32 = pci_read_config32(dev, 0x64);
270 reg32 |= 0x00100000; /* lpcEnable */
271 pci_write_config32(dev, 0x64, reg32);
273 /* Enable port 80 LPC decode in pci function 3 configuration space. */
274 dev = pci_locate_device(PCI_ID(0x1002, 0x438d), 0);
275 byte = pci_read_config8(dev, 0x4a);
276 byte |= 1 << 5; /* enable port 80 */
277 pci_write_config8(dev, 0x4a, byte);
281 /* sbDevicesPorInitTable */
282 static void sb600_devices_por_init(void)
287 printk(BIOS_INFO, "sb600_devices_por_init()\n");
288 /* SMBus Device, BDF:0-20-0 */
289 printk(BIOS_INFO, "sb600_devices_por_init(): SMBus Device, BDF:0-20-0\n");
290 dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0);
292 if (dev == PCI_DEV_INVALID) {
293 die("SMBUS controller not found\n");
296 printk(BIOS_INFO, "SMBus controller enabled, sb revision is 0x%x\n",
297 get_sb600_revision());
299 /* sbPorAtStartOfTblCfg */
300 /* Set A-Link bridge access address. This address is set at device 14h, function 0, register 0xf0.
301 * This is an I/O address. The I/O address must be on 16-byte boundry. */
302 pci_write_config32(dev, 0xf0, AB_INDX);
304 /* To enable AB/BIF DMA access, a specific register inside the BIF register space needs to be configured first. */
305 /*Enables the SB600 to send transactions upstream over A-Link Express interface. */
306 axcfg_reg(0x04, 1 << 2, 1 << 2);
307 axindxc_reg(0x21, 0xff, 0);
309 /* 2.3.5:Enabling Non-Posted Memory Write for the K8 Platform */
310 axindxc_reg(0x10, 1 << 9, 1 << 9);
311 /* END of sbPorAtStartOfTblCfg */
313 /* sbDevicesPorInitTables */
314 /* set smbus iobase */
315 pci_write_config32(dev, 0x10, SMBUS_IO_BASE | 1);
317 /* enable smbus controller interface */
318 byte = pci_read_config8(dev, 0xd2);
320 pci_write_config8(dev, 0xd2, byte);
322 /* set smbus 1, ASF 2.0 (Alert Standard Format), iobase */
323 pci_write_config16(dev, 0x58, SMBUS_IO_BASE | 0x11);
325 /* TODO: I don't know the useage of followed two lines. I copied them from CIM. */
326 pci_write_config8(dev, 0x0a, 0x1);
327 pci_write_config8(dev, 0x0b, 0x6);
330 pci_write_config8(dev, 0x40, 0xd4);
332 /* Enable ISA Address 0-960K decoding */
333 pci_write_config8(dev, 0x48, 0x0f);
335 /* Enable ISA Address 0xC0000-0xDFFFF decode */
336 pci_write_config8(dev, 0x49, 0xff);
338 /* Enable decode cycles to IO C50, C51, C52 GPM controls. */
339 byte = pci_read_config8(dev, 0x41);
342 pci_write_config8(dev, 0x41, byte);
344 /* Legacy DMA Prefetch Enhancement, CIM masked it. */
345 /* pci_write_config8(dev, 0x43, 0x1); */
347 /* Disabling Legacy USB Fast SMI# */
348 byte = pci_read_config8(dev, 0x62);
350 pci_write_config8(dev, 0x62, byte);
352 /* Features Enable */
353 pci_write_config32(dev, 0x64, 0x829E7DBF); /* bit10: Enables the HPET interrupt. */
355 /* SerialIrq Control */
356 pci_write_config8(dev, 0x69, 0x90);
358 /* Test Mode, PCIB_SReset_En Mask is set. */
359 pci_write_config8(dev, 0x6c, 0x20);
361 /* IO Address Enable, CIM set 0x78 only and masked 0x79. */
362 /*pci_write_config8(dev, 0x79, 0x4F); */
363 pci_write_config8(dev, 0x78, 0xFF);
365 /* This register is not used on sb600. It came from older chipset. */
366 /*pci_write_config8(dev, 0x95, 0xFF); */
368 /* Set smbus iospace enable, I don't know why write 0x04 into reg5 that is reserved */
369 pci_write_config16(dev, 0x4, 0x0407);
371 /* clear any lingering errors, so the transaction will run */
372 outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
374 /* IDE Device, BDF:0-20-1 */
375 printk(BIOS_INFO, "sb600_devices_por_init(): IDE Device, BDF:0-20-1\n");
376 dev = pci_locate_device(PCI_ID(0x1002, 0x438C), 0);
377 /* Disable prefetch */
378 byte = pci_read_config8(dev, 0x63);
380 pci_write_config8(dev, 0x63, byte);
382 /* LPC Device, BDF:0-20-3 */
383 printk(BIOS_INFO, "sb600_devices_por_init(): LPC Device, BDF:0-20-3\n");
384 dev = pci_locate_device(PCI_ID(0x1002, 0x438D), 0);
386 pci_write_config8(dev, 0x40, 0x04);
388 /* IO Port Decode Enable */
389 pci_write_config8(dev, 0x44, 0xFF);
390 pci_write_config8(dev, 0x45, 0xFF);
391 pci_write_config8(dev, 0x46, 0xC3);
392 pci_write_config8(dev, 0x47, 0xFF);
394 /* IO/Mem Port Decode Enable, I don't know why CIM disable some ports.
395 * Disable LPC TimeOut counter, enable SuperIO Configuration Port (2e/2f),
396 * Alternate SuperIO Configuration Port (4e/4f), Wide Generic IO Port (64/65).
397 * Enable bits for LPC ROM memory address range 1&2 for 1M ROM setting.*/
398 byte = pci_read_config8(dev, 0x48);
399 byte |= (1 << 1) | (1 << 0); /* enable Super IO config port 2e-2h, 4e-4f */
400 byte |= (1 << 3) | (1 << 4); /* enable for LPC ROM address range1&2, Enable 512KB rom access at 0xFFF80000 - 0xFFFFFFFF */
401 byte |= 1 << 6; /* enable for RTC I/O range */
402 pci_write_config8(dev, 0x48, byte);
403 pci_write_config8(dev, 0x49, 0xFF);
404 /* Enable 0x480-0x4bf, 0x4700-0x470B */
405 byte = pci_read_config8(dev, 0x4A);
406 byte |= ((1 << 1) + (1 << 6)); /*0x42, save the configuraion for port 0x80. */
407 pci_write_config8(dev, 0x4A, byte);
409 /* Set LPC ROM size, it has been done in sb600_lpc_init().
410 * enable LPC ROM range, 0xfff8: 512KB, 0xfff0: 1MB;
411 * enable LPC ROM range, 0xfff8: 512KB, 0xfff0: 1MB
412 * pci_write_config16(dev, 0x68, 0x000e)
413 * pci_write_config16(dev, 0x6c, 0xfff0);*/
415 /* Enable Tpm12_en and Tpm_legacy. I don't know what is its usage and copied from CIM. */
416 pci_write_config8(dev, 0x7C, 0x05);
418 /* P2P Bridge, BDF:0-20-4, the configuration of the registers in this dev are copied from CIM,
419 * TODO: I don't know what are their mean? */
420 printk(BIOS_INFO, "sb600_devices_por_init(): P2P Bridge, BDF:0-20-4\n");
421 dev = pci_locate_device(PCI_ID(0x1002, 0x4384), 0);
422 /* I don't know why CIM tried to write into a read-only reg! */
423 /*pci_write_config8(dev, 0x0c, 0x20) */ ;
425 /* Arbiter enable. */
426 pci_write_config8(dev, 0x43, 0xff);
428 /* Set PCDMA request into hight priority list. */
429 /* pci_write_config8(dev, 0x49, 0x1) */ ;
431 pci_write_config8(dev, 0x40, 0x26);
433 /* I don't know why CIM set reg0x1c as 0x11.
434 * System will block at sdram_initialize() if I set it before call sdram_initialize().
435 * If it is necessary to set reg0x1c as 0x11, please call this function after sdram_initialize().
436 * pci_write_config8(dev, 0x1c, 0x11);
437 * pci_write_config8(dev, 0x1d, 0x11);*/
439 /*CIM set this register; but I didn't find its description in RPR.
440 On DBM690T platform, I didn't find different between set and skip this register.
441 But on Filbert platform, the DEBUG message from serial port on Peanut board can't be displayed
442 after the bit0 of this register is set.
443 pci_write_config8(dev, 0x04, 0x21);
445 pci_write_config8(dev, 0x0d, 0x40);
446 pci_write_config8(dev, 0x1b, 0x40);
447 /* Enable PCIB_DUAL_EN_UP will fix potential problem with PCI cards. */
448 pci_write_config8(dev, 0x50, 0x01);
450 /* SATA Device, BDF:0-18-0, Non-Raid-5 SATA controller */
451 printk(BIOS_INFO, "sb600_devices_por_init(): SATA Device, BDF:0-18-0\n");
452 dev = pci_locate_device(PCI_ID(0x1002, 0x4380), 0);
454 /*PHY Global Control, we are using A14.
455 * default: 0x2c40 for ASIC revision A12 and below
456 * 0x2c00 for ASIC revision A13 and above.*/
457 pci_write_config16(dev, 0x86, 0x2C00);
459 /* PHY Port0-3 Control */
460 pci_write_config32(dev, 0x88, 0xB400DA);
461 pci_write_config32(dev, 0x8c, 0xB400DA);
462 pci_write_config32(dev, 0x90, 0xB400DA);
463 pci_write_config32(dev, 0x94, 0xB400DA);
465 /* Port0-3 BIST Control/Status */
466 pci_write_config8(dev, 0xa5, 0xB8);
467 pci_write_config8(dev, 0xad, 0xB8);
468 pci_write_config8(dev, 0xb5, 0xB8);
469 pci_write_config8(dev, 0xbd, 0xB8);
472 /* sbPmioPorInitTable, Pre-initializing PMIO register space
473 * The power management (PM) block is resident in the PCI/LPC/ISA bridge.
474 * The PM regs are accessed via IO mapped regs 0xcd6 and 0xcd7.
475 * The index address is first programmed into IO reg 0xcd6.
476 * Read or write values are accessed through IO reg 0xcd7.
478 static void sb600_pmio_por_init(void)
482 printk(BIOS_INFO, "sb600_pmio_por_init()\n");
483 /* K8KbRstEn, KB_RST# control for K8 system. */
484 byte = pmio_read(0x66);
486 pmio_write(0x66, byte);
488 /* RPR2.3.4 S3/S4/S5 Function for the K8 Platform. */
489 byte = pmio_read(0x52);
492 pmio_write(0x52, byte);
494 /* C state enable and SLP enable in C states. */
495 byte = pmio_read(0x67);
497 pmio_write(0x67, byte);
499 /* CIM sets 0x0e, but bit2 is for P4 system. */
500 byte = pmio_read(0x68);
503 pmio_write(0x68, byte);
505 /* Watch Dog Timer Control
506 * Set watchdog time base to 0xfec000f0 to avoid SCSI card boot failure.
507 * But I don't find WDT is enabled in SMBUS 0x41 bit3 in CIM.
509 pmio_write(0x6c, 0xf0);
510 pmio_write(0x6d, 0x00);
511 pmio_write(0x6e, 0xc0);
512 pmio_write(0x6f, 0xfe);
514 /* rpr2.14: Enables HPET periodical mode */
515 byte = pmio_read(0x9a);
517 pmio_write(0x9a, byte);
518 byte = pmio_read(0x9f);
520 pmio_write(0x9f, byte);
521 byte = pmio_read(0x9e);
522 byte |= (1 << 6) | (1 << 7);
523 pmio_write(0x9e, byte);
525 /* rpr2.14: Hides SM bus controller Bar1 where stores HPET MMIO base address */
526 /* We have to clear this bit here, otherwise the kernel hangs. */
527 byte = pmio_read(0x55);
530 pmio_write(0x55, byte);
532 /* rpr2.14: Make HPET MMIO decoding controlled by the memory enable bit in command register of LPC ISA bridage */
533 byte = pmio_read(0x52);
535 pmio_write(0x52, byte);
537 /* rpr2.22: PLL Reset */
538 byte = pmio_read(0x86);
540 pmio_write(0x86, byte);
543 /* This provides 16us delay before the assertion of LDTSTP# when C3 is entered.
544 * The delay will allow USB DMA to go on in a continuous manner
546 pmio_write(0x89, 0x10);
547 /* Set this bit to allow pop-up request being latched during the minimum LDTSTP# assertion time */
548 byte = pmio_read(0x52);
550 pmio_write(0x52, byte);
552 /* rpr2.15: ASF Remote Control Action */
553 byte = pmio_read(0x9f);
555 pmio_write(0x9f, byte);
557 /* rpr2.19: Enabling Spread Spectrum */
558 byte = pmio_read(0x42);
560 pmio_write(0x42, byte);
564 * Compliant with CIM_48's sbPciCfg.
565 * Add any south bridge setting.
567 static void sb600_pci_cfg(void)
572 /* SMBus Device, BDF:0-20-0 */
573 dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0);
574 /* Eable the hidden revision ID, available after A13. */
575 byte = pci_read_config8(dev, 0x70);
577 pci_write_config8(dev, 0x70, byte);
578 /* rpr2.20 Disable Timer IRQ Enhancement for proper operation of the 8254 timer, 0xae[5]. */
579 byte = pci_read_config8(dev, 0xae);
581 pci_write_config8(dev, 0xae, byte);
583 /* Enable watchdog decode timer */
584 byte = pci_read_config8(dev, 0x41);
586 pci_write_config8(dev, 0x41, byte);
588 /* Set to 1 to reset USB on the software (such as IO-64 or IO-CF9 cycles)
589 * generated PCIRST#. */
590 byte = pmio_read(0x65);
592 pmio_write(0x65, byte);
593 /*For A13 and above. */
594 if (get_sb600_revision() > 0x12) {
595 /* rpr2.16 C-State Reset, PMIO 0x9f[7]. */
596 byte = pmio_read(0x9f);
598 pmio_write(0x9f, byte);
599 /* rpr2.17 PCI Clock Period will increase to 30.8ns. 0x53[7]. */
600 byte = pmio_read(0x53);
602 pmio_write(0x53, byte);
605 /* IDE Device, BDF:0-20-1 */
606 dev = pci_locate_device(PCI_ID(0x1002, 0x438C), 0);
607 /* Enable IDE Explicit prefetch, 0x63[0] clear */
608 byte = pci_read_config8(dev, 0x63);
610 pci_write_config8(dev, 0x63, byte);
612 /* LPC Device, BDF:0-20-3 */
613 dev = pci_locate_device(PCI_ID(0x1002, 0x438D), 0);
614 /* rpr7.2 Enabling LPC DMA function. */
615 byte = pci_read_config8(dev, 0x40);
617 pci_write_config8(dev, 0x40, byte);
618 /* rpr7.3 Disabling LPC TimeOut. 0x48[7] clear. */
619 byte = pci_read_config8(dev, 0x48);
621 pci_write_config8(dev, 0x48, byte);
622 /* rpr7.5 Disabling LPC MSI Capability, 0x78[1] clear. */
623 byte = pci_read_config8(dev, 0x78);
625 pci_write_config8(dev, 0x78, byte);
627 /* SATA Device, BDF:0-18-0, Non-Raid-5 SATA controller */
628 dev = pci_locate_device(PCI_ID(0x1002, 0x4380), 0);
629 /* rpr6.8 Disabling SATA MSI Capability, for A13 and above, 0x42[7]. */
630 if (0x12 < get_sb600_revision()) {
632 reg32 = pci_read_config32(dev, 0x40);
634 pci_write_config32(dev, 0x40, reg32);
637 /* EHCI Device, BDF:0-19-5, ehci usb controller */
638 dev = pci_locate_device(PCI_ID(0x1002, 0x4386), 0);
639 /* rpr5.10 Disabling USB EHCI MSI Capability. 0x50[6]. */
640 byte = pci_read_config8(dev, 0x50);
642 pci_write_config8(dev, 0x50, byte);
644 /* OHCI0 Device, BDF:0-19-0, ohci usb controller #0 */
645 dev = pci_locate_device(PCI_ID(0x1002, 0x4387), 0);
646 /* rpr5.11 Disabling USB OHCI MSI Capability. 0x40[12:8]=0x1f. */
647 byte = pci_read_config8(dev, 0x41);
649 pci_write_config8(dev, 0x41, byte);
654 * Compliant with CIM_48's ATSBPowerOnResetInitJSP
656 static void sb600_por_init(void)
658 /* sbDevicesPorInitTable + sbK8PorInitTable */
659 sb600_devices_por_init();
661 /* sbPmioPorInitTable + sbK8PmioPorInitTable */
662 sb600_pmio_por_init();
666 * Compliant with CIM_48's AtiSbBeforePciInit
667 * It should be called during early POST after memory detection and BIOS shadowing but before PCI bus enumeration.
669 static void sb600_before_pci_init(void)
675 * This function should be called after enable_sb600_smbus().
677 static void sb600_early_setup(void)
679 printk(BIOS_INFO, "sb600_early_setup()\n");
683 static int smbus_read_byte(u32 device, u32 address)
685 return do_smbus_read_byte(SMBUS_IO_BASE, device, address);