2 * This file is part of the coreboot project.
4 * Copyright (C) 2008 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 #include "sb600_smbus.c"
24 #define SMBUS_IO_BASE 0x1000 /* Is it a temporary SMBus I/O base address? */
28 static void pmio_write(u8 reg, u8 value)
31 outb(value, PM_INDEX + 1);
34 static u8 pmio_read(u8 reg)
37 return inb(PM_INDEX + 1);
40 /* Get SB ASIC Revision.*/
41 static u8 get_sb600_revision()
44 dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0);
46 if (dev == PCI_DEV_INVALID) {
47 die("SMBUS controller not found\r\n");
50 return pci_read_config8(dev, 0x08);
54 /***************************************
55 * Legacy devices are mapped to LPC space.
58 * ACPI Micro-controller port
60 * This function does not change port 0x80 decoding.
61 * Console output through any port besides 0x3f8 is unsupported.
62 * If you use FWH ROMs, you have to setup IDSEL.
63 * NOTE: Call me ASAP, because I will reset LPC ROM size!
64 * Reviewed-by: Carl-Daniel Hailfinger
65 * Reviewed against AMD SB600 Register Reference Manual rev. 3.03, section 3.1
67 ***************************************/
68 static void sb600_lpc_init(void)
74 /* Enable lpc controller */
75 dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0); /* SMBUS controller */
76 reg32 = pci_read_config32(dev, 0x64);
78 pci_write_config32(dev, 0x64, reg32);
80 dev = pci_locate_device(PCI_ID(0x1002, 0x438d), 0); /* LPC Controller */
81 /* Decode port 0x3f8-0x3ff (Serial 0) */
82 #warning Serial port decode on LPC is hardcoded to 0x3f8
83 reg8 = pci_read_config8(dev, 0x44);
85 pci_write_config8(dev, 0x44, reg8);
87 /* Decode port 0x60 & 0x64 (PS/2 keyboard) and port 0x62 & 0x66 (ACPI)*/
88 reg8 = pci_read_config8(dev, 0x47);
89 reg8 |= (1 << 5) | (1 << 6);
90 pci_write_config8(dev, 0x47, reg8);
92 /* SuperIO, LPC ROM */
93 reg8 = pci_read_config8(dev, 0x48);
94 /* Decode ports 0x2e-0x2f, 0x4e-0x4f (SuperI/O configuration) */
95 reg8 |= (1 << 1) | (1 << 0);
96 /* Decode variable LPC ROM address ranges 1&2 (see register 0x68-0x6b, 0x6c-0x6f) */
97 reg8 |= (1 << 3) | (1 << 4);
98 /* Decode port 0x70-0x73 (RTC) */
100 pci_write_config8(dev, 0x48, reg8);
102 /* hardware should enable LPC ROM by pin straps */
103 /* ROM access at 0xFFF80000/0xFFF00000 - 0xFFFFFFFF */
104 /* See detail in BDG-215SB600-03.pdf page 15. */
105 /* enable LPC ROM range mirroring start 0x000e(0000) */
106 pci_write_config16(dev, 0x68, 0x000e);
107 /* enable LPC ROM range mirroring end 0x000f(ffff) */
108 pci_write_config16(dev, 0x6a, 0x000f);
109 /* enable LPC ROM range start, 0xfff8(0000): 512KB, 0xfff0(0000): 1MB */
110 pci_write_config16(dev, 0x6c, 0xfff0);
111 /* enable LPC ROM range end at 0xffff(ffff) */
112 pci_write_config16(dev, 0x6e, 0xffff);
115 /* what is its usage? */
116 static u32 get_sbdn(u32 bus)
120 /* Find the device. */
121 dev = pci_locate_device_on_bus(PCI_ID(0x1002, 0x4385), bus);
122 return (dev >> 15) & 0x1f;
126 static u8 dual_core()
128 if(((cpuid_eax(0x80000000) & ~0xff) >= 8)) {
129 if(cpuid_ecx(0x80000008) & 1)
136 SB600 VFSMAF (VID/FID System Management Action Field) is 010b by default.
137 RPR 2.3.3 C-state and VID/FID change for the K8 platform.
139 static void enable_fid_change_on_sb(u32 sbbusn, u32 sbdn)
142 byte = pmio_read(0x9a);
148 pmio_write(0x9a, byte);
150 byte = pmio_read(0x8f);
153 pmio_write(0x8f, byte);
155 pmio_write(0x8b, 0x01);
156 pmio_write(0x8a, 0x90);
158 if(get_sb600_revision() > 0x13)
159 pmio_write(0x88, 0x10);
161 pmio_write(0x88, 0x06);
163 byte = pmio_read(0x7c);
166 pmio_write(0x7c, byte);
168 /*Must be 0 for K8 platform.*/
169 byte = pmio_read(0x68);
171 pmio_write(0x68, byte);
172 /*Must be 0 for K8 platform.*/
173 byte = pmio_read(0x8d);
175 pmio_write(0x8d, byte);
177 byte = pmio_read(0x61);
179 pmio_write(0x61, byte);
181 byte = pmio_read(0x42);
183 pmio_write(0x42, byte);
185 if(get_sb600_revision() == 0x14) {
186 pmio_write(0x89, 0x10);
188 byte = pmio_read(0x52);
190 pmio_write(0x52, byte);
195 static void hard_reset(void)
204 static void soft_reset(void)
212 static void sb600_pci_port80()
218 dev = pci_locate_device(PCI_ID(0x1002, 0x4384), 0);
220 /* Chip Control: Enable subtractive decoding */
221 byte = pci_read_config8(dev, 0x40);
223 pci_write_config8(dev, 0x40, byte);
225 /* Misc Control: Enable subtractive decoding if 0x40 bit 5 is set */
226 byte = pci_read_config8(dev, 0x4B);
228 pci_write_config8(dev, 0x4B, byte);
230 /* The same IO Base and IO Limit here is meaningful because we set the
231 * bridge to be subtractive. During early setup stage, we have to make
232 * sure that data can go through port 0x80.
234 /* IO Base: 0xf000 */
235 byte = pci_read_config8(dev, 0x1C);
237 pci_write_config8(dev, 0x1C, byte);
239 /* IO Limit: 0xf000 */
240 byte = pci_read_config8(dev, 0x1D);
242 pci_write_config8(dev, 0x1D, byte);
244 /* PCI Command: Enable IO response */
245 byte = pci_read_config8(dev, 0x04);
247 pci_write_config8(dev, 0x04, byte);
250 dev = pci_locate_device(PCI_ID(0x1002, 0x438D), 0);
252 byte = pci_read_config8(dev, 0x4A);
253 byte &= ~(1 << 5); /* disable lpc port 80 */
254 pci_write_config8(dev, 0x4A, byte);
257 static void sb600_lpc_port80(void)
263 /* Enable LPC controller */
264 dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0);
265 reg32 = pci_read_config32(dev, 0x64);
266 reg32 |= 0x00100000; /* lpcEnable */
267 pci_write_config32(dev, 0x64, reg32);
269 /* Enable port 80 LPC decode in pci function 3 configuration space. */
270 dev = pci_locate_device(PCI_ID(0x1002, 0x438d), 0);
271 byte = pci_read_config8(dev, 0x4a);
272 byte |= 1 << 5; /* enable port 80 */
273 pci_write_config8(dev, 0x4a, byte);
277 /* sbDevicesPorInitTable */
278 static void sb600_devices_por_init()
283 printk_info("sb600_devices_por_init()\n");
284 /* SMBus Device, BDF:0-20-0 */
285 printk_info("sb600_devices_por_init(): SMBus Device, BDF:0-20-0\n");
286 dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0);
288 if (dev == PCI_DEV_INVALID) {
289 die("SMBUS controller not found\r\n");
292 printk_info("SMBus controller enabled, sb revision is 0x%x\r\n",
293 get_sb600_revision());
295 /* sbPorAtStartOfTblCfg */
296 /* Set A-Link bridge access address. This address is set at device 14h, function 0, register 0xf0.
297 * This is an I/O address. The I/O address must be on 16-byte boundry. */
298 pci_write_config32(dev, 0xf0, AB_INDX);
300 /* To enable AB/BIF DMA access, a specific register inside the BIF register space needs to be configured first. */
301 /*Enables the SB600 to send transactions upstream over A-Link Express interface. */
302 axcfg_reg(0x04, 1 << 2, 1 << 2);
303 axindxc_reg(0x21, 0xff, 0);
305 /* 2.3.5:Enabling Non-Posted Memory Write for the K8 Platform */
306 axindxc_reg(0x10, 1 << 9, 1 << 9);
307 /* END of sbPorAtStartOfTblCfg */
309 /* sbDevicesPorInitTables */
310 /* set smbus iobase */
311 pci_write_config32(dev, 0x10, SMBUS_IO_BASE | 1);
313 /* enable smbus controller interface */
314 byte = pci_read_config8(dev, 0xd2);
316 pci_write_config8(dev, 0xd2, byte);
318 /* set smbus 1, ASF 2.0 (Alert Standard Format), iobase */
319 pci_write_config16(dev, 0x58, SMBUS_IO_BASE | 0x11);
321 /* TODO: I don't know the useage of followed two lines. I copied them from CIM. */
322 pci_write_config8(dev, 0x0a, 0x1);
323 pci_write_config8(dev, 0x0b, 0x6);
326 pci_write_config8(dev, 0x40, 0xd4);
328 /* Enable ISA Address 0-960K decoding */
329 pci_write_config8(dev, 0x48, 0x0f);
331 /* Enable ISA Address 0xC0000-0xDFFFF decode */
332 pci_write_config8(dev, 0x49, 0xff);
334 /* Enable decode cycles to IO C50, C51, C52 GPM controls. */
335 byte = pci_read_config8(dev, 0x41);
338 pci_write_config8(dev, 0x41, byte);
340 /* Legacy DMA Prefetch Enhancement, CIM masked it. */
341 /* pci_write_config8(dev, 0x43, 0x1); */
343 /* Disabling Legacy USB Fast SMI# */
344 byte = pci_read_config8(dev, 0x62);
346 pci_write_config8(dev, 0x62, byte);
348 /* Features Enable */
349 pci_write_config32(dev, 0x64, 0x829E7DBF); /* bit10: Enables the HPET interrupt. */
351 /* SerialIrq Control */
352 pci_write_config8(dev, 0x69, 0x90);
354 /* Test Mode, PCIB_SReset_En Mask is set. */
355 pci_write_config8(dev, 0x6c, 0x20);
357 /* IO Address Enable, CIM set 0x78 only and masked 0x79. */
358 /*pci_write_config8(dev, 0x79, 0x4F); */
359 pci_write_config8(dev, 0x78, 0xFF);
361 /* This register is not used on sb600. It came from older chipset. */
362 /*pci_write_config8(dev, 0x95, 0xFF); */
364 /* Set smbus iospace enable, I don't know why write 0x04 into reg5 that is reserved */
365 pci_write_config16(dev, 0x4, 0x0407);
367 /* clear any lingering errors, so the transaction will run */
368 outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
370 /* IDE Device, BDF:0-20-1 */
371 printk_info("sb600_devices_por_init(): IDE Device, BDF:0-20-1\n");
372 dev = pci_locate_device(PCI_ID(0x1002, 0x438C), 0);
373 /* Disable prefetch */
374 byte = pci_read_config8(dev, 0x63);
376 pci_write_config8(dev, 0x63, byte);
378 /* LPC Device, BDF:0-20-3 */
379 printk_info("sb600_devices_por_init(): LPC Device, BDF:0-20-3\n");
380 dev = pci_locate_device(PCI_ID(0x1002, 0x438D), 0);
382 pci_write_config8(dev, 0x40, 0x04);
384 /* IO Port Decode Enable */
385 pci_write_config8(dev, 0x44, 0xFF);
386 pci_write_config8(dev, 0x45, 0xFF);
387 pci_write_config8(dev, 0x46, 0xC3);
388 pci_write_config8(dev, 0x47, 0xFF);
390 /* IO/Mem Port Decode Enable, I don't know why CIM disable some ports.
391 * Disable LPC TimeOut counter, enable SuperIO Configuration Port (2e/2f),
392 * Alternate SuperIO Configuration Port (4e/4f), Wide Generic IO Port (64/65).
393 * Enable bits for LPC ROM memory address range 1&2 for 1M ROM setting.*/
394 byte = pci_read_config8(dev, 0x48);
395 byte |= (1 << 1) | (1 << 0); /* enable Super IO config port 2e-2h, 4e-4f */
396 byte |= (1 << 3) | (1 << 4); /* enable for LPC ROM address range1&2, Enable 512KB rom access at 0xFFF80000 - 0xFFFFFFFF */
397 byte |= 1 << 6; /* enable for RTC I/O range */
398 pci_write_config8(dev, 0x48, byte);
399 pci_write_config8(dev, 0x49, 0xFF);
400 /* Enable 0x480-0x4bf, 0x4700-0x470B */
401 byte = pci_read_config8(dev, 0x4A);
402 byte |= ((1 << 1) + (1 << 6)); /*0x42, save the configuraion for port 0x80. */
403 pci_write_config8(dev, 0x4A, byte);
405 /* Set LPC ROM size, it has been done in sb600_lpc_init().
406 * enable LPC ROM range, 0xfff8: 512KB, 0xfff0: 1MB;
407 * enable LPC ROM range, 0xfff8: 512KB, 0xfff0: 1MB
408 * pci_write_config16(dev, 0x68, 0x000e)
409 * pci_write_config16(dev, 0x6c, 0xfff0);*/
411 /* Enable Tpm12_en and Tpm_legacy. I don't know what is its usage and copied from CIM. */
412 pci_write_config8(dev, 0x7C, 0x05);
414 /* P2P Bridge, BDF:0-20-4, the configuration of the registers in this dev are copied from CIM,
415 * TODO: I don't know what are their mean? */
416 printk_info("sb600_devices_por_init(): P2P Bridge, BDF:0-20-4\n");
417 dev = pci_locate_device(PCI_ID(0x1002, 0x4384), 0);
418 /* I don't know why CIM tried to write into a read-only reg! */
419 /*pci_write_config8(dev, 0x0c, 0x20) */ ;
421 /* Arbiter enable. */
422 pci_write_config8(dev, 0x43, 0xff);
424 /* Set PCDMA request into hight priority list. */
425 /* pci_write_config8(dev, 0x49, 0x1) */ ;
427 pci_write_config8(dev, 0x40, 0x26);
429 /* I don't know why CIM set reg0x1c as 0x11.
430 * System will block at sdram_initialize() if I set it before call sdram_initialize().
431 * If it is necessary to set reg0x1c as 0x11, please call this function after sdram_initialize().
432 * pci_write_config8(dev, 0x1c, 0x11);
433 * pci_write_config8(dev, 0x1d, 0x11);*/
435 /*CIM set this register; but I didn't find its description in RPR.
436 On DBM690T platform, I didn't find different between set and skip this register.
437 But on Filbert platform, the CONFIG_DEBUG message from serial port on Peanut board can't be displayed
438 after the bit0 of this register is set.
439 pci_write_config8(dev, 0x04, 0x21);
441 pci_write_config8(dev, 0x0d, 0x40);
442 pci_write_config8(dev, 0x1b, 0x40);
443 /* Enable PCIB_DUAL_EN_UP will fix potential problem with PCI cards. */
444 pci_write_config8(dev, 0x50, 0x01);
446 /* SATA Device, BDF:0-18-0, Non-Raid-5 SATA controller */
447 printk_info("sb600_devices_por_init(): SATA Device, BDF:0-18-0\n");
448 dev = pci_locate_device(PCI_ID(0x1002, 0x4380), 0);
450 /*PHY Global Control, we are using A14.
451 * default: 0x2c40 for ASIC revision A12 and below
452 * 0x2c00 for ASIC revision A13 and above.*/
453 pci_write_config16(dev, 0x86, 0x2C00);
455 /* PHY Port0-3 Control */
456 pci_write_config32(dev, 0x88, 0xB400DA);
457 pci_write_config32(dev, 0x8c, 0xB400DA);
458 pci_write_config32(dev, 0x90, 0xB400DA);
459 pci_write_config32(dev, 0x94, 0xB400DA);
461 /* Port0-3 BIST Control/Status */
462 pci_write_config8(dev, 0xa5, 0xB8);
463 pci_write_config8(dev, 0xad, 0xB8);
464 pci_write_config8(dev, 0xb5, 0xB8);
465 pci_write_config8(dev, 0xbd, 0xB8);
468 /* sbPmioPorInitTable, Pre-initializing PMIO register space
469 * The power management (PM) block is resident in the PCI/LPC/ISA bridge.
470 * The PM regs are accessed via IO mapped regs 0xcd6 and 0xcd7.
471 * The index address is first programmed into IO reg 0xcd6.
472 * Read or write values are accessed through IO reg 0xcd7.
474 static void sb600_pmio_por_init()
478 printk_info("sb600_pmio_por_init()\n");
479 /* K8KbRstEn, KB_RST# control for K8 system. */
480 byte = pmio_read(0x66);
482 pmio_write(0x66, byte);
484 /* RPR2.3.4 S3/S4/S5 Function for the K8 Platform. */
485 byte = pmio_read(0x52);
488 pmio_write(0x52, byte);
490 /* C state enable and SLP enable in C states. */
491 byte = pmio_read(0x67);
493 pmio_write(0x67, byte);
495 /* CIM sets 0x0e, but bit2 is for P4 system. */
496 byte = pmio_read(0x68);
499 pmio_write(0x68, byte);
501 /* Watch Dog Timer Control
502 * Set watchdog time base to 0xfec000f0 to avoid SCSI card boot failure.
503 * But I don't find WDT is enabled in SMBUS 0x41 bit3 in CIM.
505 pmio_write(0x6c, 0xf0);
506 pmio_write(0x6d, 0x00);
507 pmio_write(0x6e, 0xc0);
508 pmio_write(0x6f, 0xfe);
510 /* rpr2.14: Enables HPET periodical mode */
511 byte = pmio_read(0x9a);
513 pmio_write(0x9a, byte);
514 byte = pmio_read(0x9f);
516 pmio_write(0x9f, byte);
517 byte = pmio_read(0x9e);
518 byte |= (1 << 6) | (1 << 7);
519 pmio_write(0x9e, byte);
521 /* rpr2.14: Hides SM bus controller Bar1 where stores HPET MMIO base address */
522 /* We have to clear this bit here, otherwise the kernel hangs. */
523 byte = pmio_read(0x55);
526 pmio_write(0x55, byte);
528 /* rpr2.14: Make HPET MMIO decoding controlled by the memory enable bit in command register of LPC ISA bridage */
529 byte = pmio_read(0x52);
531 pmio_write(0x52, byte);
533 /* rpr2.22: PLL Reset */
534 byte = pmio_read(0x86);
536 pmio_write(0x86, byte);
539 /* This provides 16us delay before the assertion of LDTSTP# when C3 is entered.
540 * The delay will allow USB DMA to go on in a continuous manner
542 pmio_write(0x89, 0x10);
543 /* Set this bit to allow pop-up request being latched during the minimum LDTSTP# assertion time */
544 byte = pmio_read(0x52);
546 pmio_write(0x52, byte);
548 /* rpr2.15: ASF Remote Control Action */
549 byte = pmio_read(0x9f);
551 pmio_write(0x9f, byte);
553 /* rpr2.19: Enabling Spread Spectrum */
554 byte = pmio_read(0x42);
556 pmio_write(0x42, byte);
560 * Compliant with CIM_48's sbPciCfg.
561 * Add any south bridge setting.
563 static void sb600_pci_cfg()
568 /* SMBus Device, BDF:0-20-0 */
569 dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0);
570 /* Eable the hidden revision ID, available after A13. */
571 byte = pci_read_config8(dev, 0x70);
573 pci_write_config8(dev, 0x70, byte);
574 /* rpr2.20 Disable Timer IRQ Enhancement for proper operation of the 8254 timer, 0xae[5]. */
575 byte = pci_read_config8(dev, 0xae);
577 pci_write_config8(dev, 0xae, byte);
579 /* Enable watchdog decode timer */
580 byte = pci_read_config8(dev, 0x41);
582 pci_write_config8(dev, 0x41, byte);
584 /* Set to 1 to reset USB on the software (such as IO-64 or IO-CF9 cycles)
585 * generated PCIRST#. */
586 byte = pmio_read(0x65);
588 pmio_write(0x65, byte);
589 /*For A13 and above. */
590 if (get_sb600_revision() > 0x12) {
591 /* rpr2.16 C-State Reset, PMIO 0x9f[7]. */
592 byte = pmio_read(0x9f);
594 pmio_write(0x9f, byte);
595 /* rpr2.17 PCI Clock Period will increase to 30.8ns. 0x53[7]. */
596 byte = pmio_read(0x53);
598 pmio_write(0x53, byte);
601 /* IDE Device, BDF:0-20-1 */
602 dev = pci_locate_device(PCI_ID(0x1002, 0x438C), 0);
603 /* Enable IDE Explicit prefetch, 0x63[0] clear */
604 byte = pci_read_config8(dev, 0x63);
606 pci_write_config8(dev, 0x63, byte);
608 /* LPC Device, BDF:0-20-3 */
609 dev = pci_locate_device(PCI_ID(0x1002, 0x438D), 0);
610 /* rpr7.2 Enabling LPC DMA function. */
611 byte = pci_read_config8(dev, 0x40);
613 pci_write_config8(dev, 0x40, byte);
614 /* rpr7.3 Disabling LPC TimeOut. 0x48[7] clear. */
615 byte = pci_read_config8(dev, 0x48);
617 pci_write_config8(dev, 0x48, byte);
618 /* rpr7.5 Disabling LPC MSI Capability, 0x78[1] clear. */
619 byte = pci_read_config8(dev, 0x78);
621 pci_write_config8(dev, 0x78, byte);
623 /* SATA Device, BDF:0-18-0, Non-Raid-5 SATA controller */
624 dev = pci_locate_device(PCI_ID(0x1002, 0x4380), 0);
625 /* rpr6.8 Disabling SATA MSI Capability, for A13 and above, 0x42[7]. */
626 if (0x12 < get_sb600_revision()) {
628 reg32 = pci_read_config32(dev, 0x40);
630 pci_write_config32(dev, 0x40, reg32);
633 /* EHCI Device, BDF:0-19-5, ehci usb controller */
634 dev = pci_locate_device(PCI_ID(0x1002, 0x4386), 0);
635 /* rpr5.10 Disabling USB EHCI MSI Capability. 0x50[6]. */
636 byte = pci_read_config8(dev, 0x50);
638 pci_write_config8(dev, 0x50, byte);
640 /* OHCI0 Device, BDF:0-19-0, ohci usb controller #0 */
641 dev = pci_locate_device(PCI_ID(0x1002, 0x4387), 0);
642 /* rpr5.11 Disabling USB OHCI MSI Capability. 0x40[12:8]=0x1f. */
643 byte = pci_read_config8(dev, 0x41);
645 pci_write_config8(dev, 0x41, byte);
650 * Compliant with CIM_48's ATSBPowerOnResetInitJSP
652 static void sb600_por_init()
654 /* sbDevicesPorInitTable + sbK8PorInitTable */
655 sb600_devices_por_init();
657 /* sbPmioPorInitTable + sbK8PmioPorInitTable */
658 sb600_pmio_por_init();
662 * Compliant with CIM_48's AtiSbBeforePciInit
663 * It should be called during early POST after memory detection and BIOS shadowing but before PCI bus enumeration.
665 static void sb600_before_pci_init()
671 * This function should be called after enable_sb600_smbus().
673 static void sb600_early_setup(void)
675 printk_info("sb600_early_setup()\n");
679 static int smbus_read_byte(u32 device, u32 address)
681 return do_smbus_read_byte(SMBUS_IO_BASE, device, address);