2 * This file is part of the coreboot project.
4 * Copyright (C) 2008 Advanced Micro Devices, Inc.
5 * Copyright (C) 2008 Carl-Daniel Hailfinger
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 #include <console/console.h>
22 #include <device/device.h>
24 #include <device/pci.h>
25 #include <device/pci_ids.h>
26 #include <device/pci_ops.h>
30 static int sata_drive_detect(int portnum, u16 iobar)
34 outb(0xA0 + 0x10 * (portnum % 2), iobar + 0x6);
35 while (byte = inb(iobar + 0x6), byte2 = inb(iobar + 0x7),
36 (byte != (0xA0 + 0x10 * (portnum % 2))) ||
37 ((byte2 & 0x88) != 0)) {
38 printk(BIOS_SPEW, "0x6=%x, 0x7=%x\n", byte, byte2);
39 if (byte != (0xA0 + 0x10 * (portnum % 2))) {
40 /* This will happen at the first iteration of this loop
41 * if the first SATA port is unpopulated and the
42 * second SATA port is populated.
44 printk(BIOS_DEBUG, "drive no longer selected after %i ms, "
45 "retrying init\n", i * 10);
48 printk(BIOS_SPEW, "drive detection not yet completed, "
53 printk(BIOS_SPEW, "drive detection done after %i ms\n", i * 10);
57 static void sata_init(struct device *dev)
63 u16 sata_bar0, sata_bar1, sata_bar2, sata_bar3, sata_bar4;
66 struct southbridge_ati_sb600_config *conf;
67 conf = dev->chip_info;
70 /* SATA SMBus Disable */
71 /* sm_dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0); */
72 sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
73 /* Disable SATA SMBUS */
74 byte = pci_read_config8(sm_dev, 0xad);
76 /* Enable SATA and power saving */
77 byte = pci_read_config8(sm_dev, 0xad);
80 pci_write_config8(sm_dev, 0xad, byte);
81 /* Set the interrupt Mapping to INTG# */
82 byte = pci_read_config8(sm_dev, 0xaf);
84 pci_write_config8(sm_dev, 0xaf, byte);
86 /* get base address */
87 sata_bar5 = pci_read_config32(dev, 0x24) & ~0x3FF;
88 sata_bar0 = pci_read_config16(dev, 0x10) & ~0x7;
89 sata_bar1 = pci_read_config16(dev, 0x14) & ~0x3;
90 sata_bar2 = pci_read_config16(dev, 0x18) & ~0x7;
91 sata_bar3 = pci_read_config16(dev, 0x1C) & ~0x3;
92 sata_bar4 = pci_read_config16(dev, 0x20) & ~0xf;
94 printk(BIOS_SPEW, "sata_bar0=%x\n", sata_bar0); /* 3030 */
95 printk(BIOS_SPEW, "sata_bar1=%x\n", sata_bar1); /* 3070 */
96 printk(BIOS_SPEW, "sata_bar2=%x\n", sata_bar2); /* 3040 */
97 printk(BIOS_SPEW, "sata_bar3=%x\n", sata_bar3); /* 3080 */
98 printk(BIOS_SPEW, "sata_bar4=%x\n", sata_bar4); /* 3000 */
99 printk(BIOS_SPEW, "sata_bar5=%x\n", sata_bar5); /* e0309000 */
101 /* Program the 2C to 0x43801002 */
103 pci_write_config32(dev, 0x2c, dword);
106 word = pci_read_config16(dev, 0x04);
108 pci_write_config16(dev, 0x04, word);
110 /* Dynamic power saving */
111 byte = pci_read_config8(dev, 0x40);
113 pci_write_config8(dev, 0x40, byte);
115 /* Set SATA Operation Mode, Set to IDE mode */
116 byte = pci_read_config8(dev, 0x40);
119 pci_write_config8(dev, 0x40, byte);
122 pci_write_config32(dev, 0x8, dword);
124 byte = pci_read_config8(dev, 0x40);
126 pci_write_config8(dev, 0x40, byte);
128 /* Enable the SATA watchdog counter */
129 byte = pci_read_config8(dev, 0x44);
131 pci_write_config8(dev, 0x44, byte);
133 /* Program the watchdog counter to 0x10 */
135 pci_write_config8(dev, 0x46, byte);
137 /* RPR6.5 Program the PHY Global Control to 0x2C00 for A13 */
139 pci_write_config16(dev, 0x86, word);
141 /* RPR6.5 Program the Phy Tuning4Ports */
143 pci_write_config32(dev, 0x88, dword);
144 pci_write_config32(dev, 0x8c, dword);
145 pci_write_config32(dev, 0x90, dword);
146 pci_write_config32(dev, 0x94, dword);
149 pci_write_config8(dev, 0xA5, byte);
150 pci_write_config8(dev, 0xAD, byte);
151 pci_write_config8(dev, 0xB5, byte);
152 pci_write_config8(dev, 0xBD, byte);
155 word = pci_read_config16(dev, 0x42);
157 pci_write_config16(dev, 0x42, word);
159 dword = pci_read_config32(dev, 0x40);
161 pci_write_config32(dev, 0x40, dword);
163 /* Enable the I/O, MM, BusMaster access for SATA */
164 byte = pci_read_config8(dev, 0x4);
166 pci_write_config8(dev, 0x4, byte);
168 /* RPR6.6 SATA drive detection. */
169 /* Use BAR5+0x128,BAR0 for Primary Slave */
170 /* Use BAR5+0x1A8,BAR0 for Primary Slave */
171 /* Use BAR5+0x228,BAR2 for Secondary Master */
172 /* Use BAR5+0x2A8,BAR2 for Secondary Slave */
174 for (i = 0; i < 4; i++) {
175 byte = read8(sata_bar5 + 0x128 + 0x80 * i);
176 printk(BIOS_SPEW, "SATA port %i status = %x\n", i, byte);
180 /* If the drive status is 0x1 then we see it but we aren't talking to it. */
181 /* Try to do something about it. */
182 printk(BIOS_SPEW, "SATA device detected but not talking. Trying lower speed.\n");
184 /* Read in Port-N Serial ATA Control Register */
185 byte = read8(sata_bar5 + 0x12C + 0x80 * i);
187 /* Set Reset Bit and 1.5g bit */
189 write8((sata_bar5 + 0x12C + 0x80 * i), byte);
194 /* Clear Reset Bit */
196 write8((sata_bar5 + 0x12C + 0x80 * i), byte);
202 byte = read8(sata_bar5 + 0x128 + 0x80 * i);
203 printk(BIOS_SPEW, "SATA port %i status = %x\n", i, byte);
208 for (j = 0; j < 10; j++) {
209 if (!sata_drive_detect(i, ((i / 2) == 0) ? sata_bar0 : sata_bar2))
212 printk(BIOS_DEBUG, "%s %s device is %sready after %i tries\n",
213 (i / 2) ? "Secondary" : "Primary",
214 (i % 2 ) ? "Slave" : "Master",
215 (j == 10) ? "not " : "",
216 (j == 10) ? j : j + 1);
218 printk(BIOS_DEBUG, "No %s %s SATA drive on Slot%i\n",
219 (i / 2) ? "Secondary" : "Primary",
220 (i % 2 ) ? "Slave" : "Master", i);
224 /* Below is CIM InitSataLateFar */
225 /* Enable interrupts from the HBA */
226 byte = read8(sata_bar5 + 0x4);
228 write8((sata_bar5 + 0x4), byte);
230 /* Clear error status */
231 write32((sata_bar5 + 0x130), 0xFFFFFFFF);
232 write32((sata_bar5 + 0x1b0), 0xFFFFFFFF);
233 write32((sata_bar5 + 0x230), 0xFFFFFFFF);
234 write32((sata_bar5 + 0x2b0), 0xFFFFFFFF);
236 /* Clear SATA status,Firstly we get the AcpiGpe0BlkAddr */
237 /* ????? why CIM does not set the AcpiGpe0BlkAddr , but use it??? */
240 /* word = pm_ioread(0x28); */
241 /* byte = pm_ioread(0x29); */
242 /* word |= byte<<8; */
243 /* printk(BIOS_DEBUG, "AcpiGpe0Blk addr = %x\n", word); */
244 /* write32(word, 0x80000000); */
247 static struct pci_operations lops_pci = {
248 /* .set_subsystem = pci_dev_set_subsystem, */
251 static struct device_operations sata_ops = {
252 .read_resources = pci_dev_read_resources,
253 .set_resources = pci_dev_set_resources,
254 .enable_resources = pci_dev_enable_resources,
255 /* .enable = sb600_enable, */
258 .ops_pci = &lops_pci,
261 static const struct pci_driver sata0_driver __pci_driver = {
263 .vendor = PCI_VENDOR_ID_ATI,
264 .device = PCI_DEVICE_ID_ATI_SB600_SATA,