2 * This file is part of the coreboot project.
4 * Copyright (C) 2010 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 * for rs780 internal graphics device
22 * device id of internal grphics:
28 * RS785G: 0x9710 - just works, not much tested
30 #include <console/console.h>
31 #include <device/device.h>
32 #include <device/pci.h>
33 #include <device/pci_ids.h>
34 #include <device/pci_ops.h>
36 #include <cpu/x86/msr.h>
38 extern int is_dev3_present(void);
39 void set_pcie_reset(void);
40 void set_pcie_dereset(void);
42 /* Trust the original resource allocation. Don't do it again. */
43 #undef DONT_TRUST_RESOURCE_ALLOCATION
44 //#define DONT_TRUST_RESOURCE_ALLOCATION
46 #define CLK_CNTL_INDEX 0x8
47 #define CLK_CNTL_DATA 0xC
49 /* The Integrated Info Table. */
50 ATOM_INTEGRATED_SYSTEM_INFO_V2 vgainfo;
53 static u32 clkind_read(device_t dev, u32 index)
55 u32 gfx_bar2 = pci_read_config32(dev, 0x18) & ~0xF;
57 *(u32*)(gfx_bar2+CLK_CNTL_INDEX) = index & 0x7F;
58 return *(u32*)(gfx_bar2+CLK_CNTL_DATA);
62 static void clkind_write(device_t dev, u32 index, u32 data)
64 u32 gfx_bar2 = pci_read_config32(dev, 0x18) & ~0xF;
65 /* printk(BIOS_DEBUG, "gfx bar 2 %02x\n", gfx_bar2); */
67 *(u32*)(gfx_bar2+CLK_CNTL_INDEX) = index | 1<<7;
68 *(u32*)(gfx_bar2+CLK_CNTL_DATA) = data;
72 * pci_dev_read_resources thinks it is a IO type.
73 * We have to force it to mem type.
75 static void rs780_gfx_read_resources(device_t dev)
77 printk(BIOS_DEBUG, "rs780_gfx_read_resources.\n");
79 /* The initial value of 0x24 is 0xFFFFFFFF, which is confusing.
80 Even if we write 0xFFFFFFFF into it, it will be 0xFFF00000,
81 which tells us it is a memory address base.
83 pci_write_config32(dev, 0x24, 0x00000000);
85 /* Get the normal pci resources of this device */
86 pci_dev_read_resources(dev);
87 compact_resources(dev);
90 typedef struct _MMIORANGE
97 MMIORANGE MMIO[8], CreativeMMIO[8];
99 #define CIM_STATUS u32
100 #define CIM_SUCCESS 0x00000000
101 #define CIM_ERROR 0x80000000
102 #define CIM_UNSUPPORTED 0x80000001
103 #define CIM_DISABLEPORT 0x80000002
105 #define MMIO_ATTRIB_NP_ONLY 1
106 #define MMIO_ATTRIB_BOTTOM_TO_TOP 1<<1
107 #define MMIO_ATTRIB_SKIP_ZERO 1<<2
109 #ifdef DONT_TRUST_RESOURCE_ALLOCATION
110 static MMIORANGE* AllocMMIO(MMIORANGE* pMMIO)
113 for (i=0; i<8; i++) {
114 if (pMMIO[i].Limit == 0)
120 static void FreeMMIO(MMIORANGE* pMMIO)
126 static u32 SetMMIO(u32 Base, u32 Limit, u8 Attribute, MMIORANGE *pMMIO)
129 MMIORANGE * TempRange;
132 if(pMMIO[i].Attribute != Attribute && Base >= pMMIO[i].Base && Limit <= pMMIO[i].Limit)
134 TempRange = AllocMMIO(pMMIO);
135 if(TempRange == 0) return 0x80000000;
136 TempRange->Base = Limit;
137 TempRange->Limit = pMMIO[i].Limit;
138 TempRange->Attribute = pMMIO[i].Attribute;
139 pMMIO[i].Limit = Base;
142 TempRange = AllocMMIO(pMMIO);
143 if(TempRange == 0) return 0x80000000;
144 TempRange->Base = Base;
145 TempRange->Limit = Limit;
146 TempRange->Attribute = Attribute;
150 static u8 FinalizeMMIO(MMIORANGE *pMMIO)
155 if (pMMIO[i].Base == pMMIO[i].Limit)
162 if (i!=j && pMMIO[i].Attribute == pMMIO[j].Attribute)
164 if (pMMIO[i].Base == pMMIO[j].Limit)
166 pMMIO[j].Limit = pMMIO[i].Limit;
169 if (pMMIO[i].Limit == pMMIO[j].Base)
171 pMMIO[j].Base = pMMIO[i].Base;
179 if (pMMIO[i].Limit != 0) n++;
184 static CIM_STATUS GetCreativeMMIO(MMIORANGE *pMMIO)
186 CIM_STATUS Status = CIM_UNSUPPORTED;
187 u8 Bus, Dev, Reg, BusStart, BusEnd;
189 device_t dev0x14 = dev_find_slot(0, PCI_DEVFN(0x14, 4));
191 Value = pci_read_config32(dev0x14, 0x18);
192 BusStart = (Value >> 8) & 0xFF;
193 BusEnd = (Value >> 16) & 0xFF;
194 for(Bus = BusStart; Bus <= BusEnd; Bus++)
196 for(Dev = 0; Dev <= 0x1f; Dev++)
198 tempdev = dev_find_slot(Bus, Dev << 3);
199 Value = pci_read_config32(tempdev, 0);
200 printk(BIOS_DEBUG, "Dev ID %x \n", Value);
201 if((Value & 0xffff) == 0x1102)
204 u32 MMIOStart = 0xffffffff;
206 for(Reg = 0x10; Reg < 0x20; Reg+=4)
209 BaseA = pci_read_config32(tempdev, Reg);
213 Value = Value & 0xffffff00;
216 if(MMIOStart > Value)
219 //WritePCI(PciAddress,AccWidthUint32,&LimitA);
220 pci_write_config32(tempdev, Reg, LimitA);
221 //ReadPCI(PciAddress,AccWidthUint32,&LimitA);
222 LimitA = pci_read_config32(tempdev, Reg);
223 LimitA = Value + (~LimitA + 1);
224 //WritePCI(PciAddress,AccWidthUint32,&BaseA);
225 pci_write_config32(tempdev, Reg, BaseA);
226 if (LimitA > MMIOLimit)
231 printk(BIOS_DEBUG, " MMIOStart %x MMIOLimit %x \n", MMIOStart, MMIOLimit);
232 if (MMIOStart < MMIOLimit)
234 Status = SetMMIO(MMIOStart>>8, MMIOLimit>>8, 0x80, pMMIO);
235 if(Status == CIM_ERROR) return Status;
240 if(Status == CIM_SUCCESS)
243 if(FinalizeMMIO(pMMIO) > 4)
252 static void ProgramMMIO(MMIORANGE *pMMIO, u8 LinkID, u8 Attribute)
257 k8_f1 = dev_find_slot(0, PCI_DEVFN(0x18, 1));
259 for(i = 0; i < 8; i++)
264 for(j = 0; j < 8; j++)
266 if (Base < pMMIO[j].Base)
268 Base = pMMIO[j].Base;
272 if(pMMIO[k].Limit != 0)
274 if(Attribute & MMIO_ATTRIB_NP_ONLY && pMMIO[k].Attribute == 0 )
280 Base = pMMIO[k].Base | 0x3;
281 Limit= ((pMMIO[k].Limit - 1) & 0xffffff00) | pMMIO[k].Attribute | (LinkID << 4);
285 if (Attribute & MMIO_ATTRIB_SKIP_ZERO && Base == 0 && Limit == 0) continue;
286 MmioReg = (Attribute & MMIO_ATTRIB_BOTTOM_TO_TOP)?n:(7-n);
288 //RWPCI(PCI_ADDRESS(0,CPU_DEV,CPU_F1,0x80+MmioReg*8),AccWidthUint32 |S3_SAVE,0x0,0x0);
289 pci_write_config32(k8_f1, 0x80+MmioReg*8, 0);
291 //WritePCI(PCI_ADDRESS(0,CPU_DEV,CPU_F1,0x84+MmioReg*8),AccWidthUint32 |S3_SAVE,&Limit);
292 pci_write_config32(k8_f1, 0x84+MmioReg*8, Limit);
294 //WritePCI(PCI_ADDRESS(0,CPU_DEV,CPU_F1,0x80+MmioReg*8),AccWidthUint32 |S3_SAVE,&Base);
295 pci_write_config32(k8_f1, 0x80+MmioReg*8, Base);
300 static void internal_gfx_pci_dev_init(struct device *dev)
302 unsigned char * bpointer;
303 volatile u32 * GpuF0MMReg;
304 volatile u32 * pointer;
308 u16 deviceid, vendorid;
309 device_t nb_dev = dev_find_slot(0, 0);
310 device_t k8_f2 = dev_find_slot(0, PCI_DEVFN(0x18, 2));
311 device_t k8_f0 = dev_find_slot(0, PCI_DEVFN(0x18, 0));
313 /* We definetely will use this in future. Just leave it here. */
314 /*struct southbridge_amd_rs780_config *cfg =
315 (struct southbridge_amd_rs780_config *)dev->chip_info;*/
317 deviceid = pci_read_config16(dev, PCI_DEVICE_ID);
318 vendorid = pci_read_config16(dev, PCI_VENDOR_ID);
319 printk(BIOS_DEBUG, "internal_gfx_pci_dev_init device=%x, vendor=%x.\n",
322 command = pci_read_config16(dev, 0x04);
324 pci_write_config16(dev, 0x04, command);
327 bpointer = (unsigned char *) &vgainfo;
328 for(i=0; i<sizeof(ATOM_INTEGRATED_SYSTEM_INFO_V2); i++)
334 GpuF0MMReg = (u32 *)pci_read_config32(dev, 0x18);
336 /* GFX_InitFBAccess. */
337 value = nbmc_read_index(nb_dev, 0x10);
338 *(GpuF0MMReg + 0x2000/4) = 0x11;
339 *(GpuF0MMReg + 0x2180/4) = ((value&0xff00)>>8)|((value&0xff000000)>>8);
340 *(GpuF0MMReg + 0x2c04/4) = ((value&0xff00)<<8);
341 *(GpuF0MMReg + 0x5428/4) = ((value&0xffff0000)+0x10000)-((value&0xffff)<<16);
342 *(GpuF0MMReg + 0x2000/4) = 0x00000011;
343 *(GpuF0MMReg + 0x200c/4) = 0x00000020;
344 *(GpuF0MMReg + 0x2010/4) = 0x10204810;
345 *(GpuF0MMReg + 0x2010/4) = 0x00204810;
346 *(GpuF0MMReg + 0x2014/4) = 0x10408810;
347 *(GpuF0MMReg + 0x2014/4) = 0x00408810;
348 *(GpuF0MMReg + 0x2414/4) = 0x00000080;
349 *(GpuF0MMReg + 0x2418/4) = 0x84422415;
350 *(GpuF0MMReg + 0x2418/4) = 0x04422415;
351 *(GpuF0MMReg + 0x5490/4) = 0x00000001;
352 *(GpuF0MMReg + 0x7de4/4) |= (1<<3) | (1<<4);
353 /* Force allow LDT_STOP Cool'n'Quiet workaround. */
354 *(GpuF0MMReg + 0x655c/4) |= 1<<4;
355 /* GFX_InitFBAccess finished. */
358 #if (CONFIG_GFXUMA == 1) /* for UMA mode. */
359 /* MC_INIT_COMPLETE. */
360 set_nbmc_enable_bits(nb_dev, 0x2, 0, 1<<31);
361 /* MC_STARTUP, MC_POWERED_UP and MC_VMODE.*/
362 set_nbmc_enable_bits(nb_dev, 0x1, 1<<18, 1|1<<2);
364 set_nbmc_enable_bits(nb_dev, 0xb1, 0, 1<<6);
365 set_nbmc_enable_bits(nb_dev, 0xc3, 0, 1);
366 nbmc_write_index(nb_dev, 0x07, 0x18);
367 nbmc_write_index(nb_dev, 0x06, 0x00000102);
368 nbmc_write_index(nb_dev, 0x09, 0x40000008);
369 set_nbmc_enable_bits(nb_dev, 0x6, 0, 1<<31);
370 /* GFX_StartMC finished. */
373 set_nbmc_enable_bits(nb_dev, 0xaa, 0xf0, 0x30);
374 set_nbmc_enable_bits(nb_dev, 0xce, 0xf0, 0x30);
375 set_nbmc_enable_bits(nb_dev, 0xca, 0xff000000, 0x47000000);
376 set_nbmc_enable_bits(nb_dev, 0xcb, 0x3f000000, 0x01000000);
377 set_nbmc_enable_bits(nb_dev, 0x01, 0, 1<<0);
378 set_nbmc_enable_bits(nb_dev, 0x04, 0, 1<<31);
379 set_nbmc_enable_bits(nb_dev, 0xb4, 0x3f, 0x3f);
380 set_nbmc_enable_bits(nb_dev, 0xb4, 0, 1<<6);
381 set_nbmc_enable_bits(nb_dev, 0xc3, 1<<11, 0);
382 set_nbmc_enable_bits(nb_dev, 0xa0, 1<<29, 0);
383 nbmc_write_index(nb_dev, 0xa4, 0x3484576f);
384 nbmc_write_index(nb_dev, 0xa5, 0x222222df);
385 nbmc_write_index(nb_dev, 0xa6, 0x00000000);
386 nbmc_write_index(nb_dev, 0xa7, 0x00000000);
387 set_nbmc_enable_bits(nb_dev, 0xc3, 1<<8, 0);
389 set_nbmc_enable_bits(nb_dev, 0xc3, 1<<9, 0);
391 set_nbmc_enable_bits(nb_dev, 0x01, 0, 1<<2);
393 set_nbmc_enable_bits(nb_dev, 0x01, 0, 1<<3);
394 set_nbmc_enable_bits(nb_dev, 0xa0, 0, 1<<31);
396 set_nbmc_enable_bits(nb_dev, 0x02, 0, 1<<31);
397 set_nbmc_enable_bits(nb_dev, 0xa0, 0, 1<<30);
398 set_nbmc_enable_bits(nb_dev, 0xa0, 1<<31, 0);
399 set_nbmc_enable_bits(nb_dev, 0xa0, 0, 1<<29);
400 nbmc_write_index(nb_dev, 0xa4, 0x23484576);
401 nbmc_write_index(nb_dev, 0xa5, 0x00000000);
402 nbmc_write_index(nb_dev, 0xa6, 0x00000000);
403 nbmc_write_index(nb_dev, 0xa7, 0x00000000);
404 /* GFX_StartMC finished. */
406 /* GFX_SPPowerManagment, don't care for new. */
407 /* Post MC Init table programming. */
408 set_nbmc_enable_bits(nb_dev, 0xac, ~(0xfffffff0), 0x0b);
410 /* Do we need Write and Read Calibration? */
411 /* GFX_Init finished. */
414 /* GFX_InitIntegratedInfo. */
415 /* fill the Integrated Info Table. */
416 vgainfo.sHeader.usStructureSize = sizeof(ATOM_INTEGRATED_SYSTEM_INFO_V2);
417 vgainfo.sHeader.ucTableFormatRevision = 1;
418 vgainfo.sHeader.ucTableContentRevision = 2;
420 #if (CONFIG_GFXUMA == 0) /* SP mode. */
421 vgainfo.ulBootUpSidePortClock = 667*100;
422 vgainfo.ucMemoryType = 3;
423 vgainfo.ulMinSidePortClock = 333*100;
426 vgainfo.ulBootUpEngineClock = 500 * 100; /* set boot up GFX engine clock. */
427 vgainfo.ulReserved1[0] = 0; vgainfo.ulReserved1[1] = 0;
428 value = pci_read_config32(k8_f2, 0x94);
429 printk(BIOS_DEBUG, "MEMCLK = %x\n", value&0x7);
430 vgainfo.ulBootUpUMAClock = 333 * 100; /* set boot up UMA memory clock. */
431 vgainfo.ulBootUpSidePortClock = 0; /* disable SP. */
432 vgainfo.ulMinSidePortClock = 0; /* disable SP. */
434 vgainfo.ulReserved2[i] = 0;
435 vgainfo.ulSystemConfig = 0;
436 //vgainfo.ulSystemConfig |= 1<<1 | 1<<3 | 1<<4 | 1<<5 | 1<<6 | 1<<7 | 1;
437 vgainfo.ulBootUpReqDisplayVector = 0; //?
438 vgainfo.ulOtherDisplayMisc = 0; //?
439 vgainfo.ulDDISlot1Config = 0x000c0011; //0; //VGA
440 //vgainfo.ulDDISlot1Config = 0x000c00FF; //0; //HDMI
441 vgainfo.ulDDISlot2Config = 0x00130022; //0; //?
442 vgainfo.ucMemoryType = 2;
443 /* UMA Channel Number: 1 or 2. */
444 vgainfo.ucUMAChannelNumber = 2;
445 vgainfo.ucDockingPinBit = 0; //?
446 vgainfo.ucDockingPinPolarity = 0; //?
447 vgainfo.ulDockingPinCFGInfo = 0; //?
448 vgainfo.ulCPUCapInfo = 3; /* K8. */
450 /* page 5-19 on BDG. */
451 vgainfo.usNumberOfCyclesInPeriod = 0x8019;
452 vgainfo.usMaxNBVoltage = 0x1a;
453 vgainfo.usMinNBVoltage = 0;
454 vgainfo.usBootUpNBVoltage = 0x1a;
456 value = pci_read_config32(nb_dev, 0xd0);
457 printk(BIOS_DEBUG, "NB HT speed = %x.\n", value);
458 value = pci_read_config32(k8_f0, 0x88);
459 printk(BIOS_DEBUG, "CPU HT speed = %x.\n", value);
460 vgainfo.ulHTLinkFreq = 100 * 100; /* set HT speed. */
463 value = pci_read_config32(nb_dev, 0xc8);
464 printk(BIOS_DEBUG, "HT width = %x.\n", value);
465 vgainfo.usMinHTLinkWidth = 16;
466 vgainfo.usMaxHTLinkWidth = 16;
467 vgainfo.usUMASyncStartDelay = 322;
468 vgainfo.usUMADataReturnTime = 86;
469 vgainfo.usLinkStatusZeroTime = 0x00c8; //0; //?
470 vgainfo.usReserved = 0;
471 vgainfo.ulHighVoltageHTLinkFreq = 100 * 100;
472 vgainfo.ulLowVoltageHTLinkFreq = 100 * 100;
473 vgainfo.usMaxUpStreamHTLinkWidth = 16;
474 vgainfo.usMaxDownStreamHTLinkWidth = 16;
475 vgainfo.usMinUpStreamHTLinkWidth = 16;
476 vgainfo.usMinDownStreamHTLinkWidth = 16;
478 vgainfo.ulReserved3[i] = 0;
480 /* Transfer the Table to VBIOS. */
481 pointer = (u32 *)&vgainfo;
482 for(i=0; i<sizeof(ATOM_INTEGRATED_SYSTEM_INFO_V2); i+=4)
484 #if (CONFIG_GFXUMA == 1)
485 *GpuF0MMReg = 0x80000000 + 0x10000000 - 512 + i;
487 *GpuF0MMReg = 0x80000000 + 0x8000000 - 512 + i;
489 *(GpuF0MMReg+1) = *pointer++;
495 temp8 = pci_read_config8(dev, 0x4);
496 //temp8 &= ~1; /* CIM clears this bit. Strangely, I can'd. */
498 pci_write_config8(dev, 0x4, temp8);
501 #ifdef DONT_TRUST_RESOURCE_ALLOCATION
502 /* NB_SetupMGMMIO. */
504 /* clear MMIO and CreativeMMIO. */
505 bpointer = (unsigned char *)MMIO;
506 for(i=0; i<sizeof(MMIO); i++)
511 bpointer = (unsigned char *)CreativeMMIO;
512 for(i=0; i<sizeof(CreativeMMIO); i++)
518 /* Set MMIO ranges in K8. */
519 /* Set MMIO TOM - 4G. */
520 SetMMIO(0x400<<12, 0x1000000, 0x80, &MMIO[0]);
521 /* Set MMIO for VGA Legacy FB. */
522 SetMMIO(0xa00, 0xc00, 0x80, &MMIO[0]);
524 /* Set MMIO for non prefetchable P2P. */
525 temp = pci_read_config32(dev0x14, 0x20);
526 Base32 = (temp & 0x0fff0) << 8;
527 Limit32 = ((temp & 0x0fff00000) + 0x100000) >> 8;
530 Status = GetCreativeMMIO(&CreativeMMIO[0]);
531 if(Status != CIM_ERROR)
532 SetMMIO(Base32, Limit32, 0x0, &MMIO[0]);
534 /* Set MMIO for prefetchable P2P. */
535 if(Status != CIM_ERROR)
537 temp = pci_read_config32(dev0x14, 0x24);
539 Base32 = (temp & 0x0fff0) <<8;
540 Limit32 = ((temp & 0x0fff00000) + 0x100000) >> 8;
542 SetMMIO(Base32, Limit32, 0x0, &MMIO[0]);
545 FinalizeMMIO(&MMIO[0]);
547 ProgramMMIO(&CreativeMMIO[0], 0, MMIO_ATTRIB_NP_ONLY);
548 ProgramMMIO(&MMIO[0], 0, MMIO_ATTRIB_NP_ONLY | MMIO_ATTRIB_BOTTOM_TO_TOP | MMIO_ATTRIB_SKIP_ZERO);
554 clkind_write(dev, 0x08, 0x01);
555 clkind_write(dev, 0x0C, 0x22);
556 clkind_write(dev, 0x0F, 0x0);
557 clkind_write(dev, 0x11, 0x0);
558 clkind_write(dev, 0x12, 0x0);
559 clkind_write(dev, 0x14, 0x0);
560 clkind_write(dev, 0x15, 0x0);
561 clkind_write(dev, 0x16, 0x0);
562 clkind_write(dev, 0x17, 0x0);
563 clkind_write(dev, 0x18, 0x0);
564 clkind_write(dev, 0x19, 0x0);
565 clkind_write(dev, 0x1A, 0x0);
566 clkind_write(dev, 0x1B, 0x0);
567 clkind_write(dev, 0x1C, 0x0);
568 clkind_write(dev, 0x1D, 0x0);
569 clkind_write(dev, 0x1E, 0x0);
570 clkind_write(dev, 0x26, 0x0);
571 clkind_write(dev, 0x27, 0x0);
572 clkind_write(dev, 0x28, 0x0);
573 clkind_write(dev, 0x5C, 0x0);
578 * Set registers in RS780 and CPU to enable the internal GFX.
579 * Please refer to CIM source code and BKDG.
581 extern uint64_t uma_memory_base, uma_memory_size;
583 static void rs780_internal_gfx_enable(device_t dev)
587 device_t nb_dev = dev_find_slot(0, 0);
590 #if (CONFIG_GFXUMA == 0)
591 u32 FB_Start, FB_End;
594 printk(BIOS_DEBUG, "rs780_internal_gfx_enable dev = 0x%p, nb_dev = 0x%p.\n", dev, nb_dev);
596 sysmem = rdmsr(0xc001001a);
597 printk(BIOS_DEBUG, "sysmem = %x_%x\n", sysmem.hi, sysmem.lo);
599 /* The system top memory in 780. */
600 pci_write_config32(nb_dev, 0x90, sysmem.lo);
601 htiu_write_index(nb_dev, 0x30, 0);
602 htiu_write_index(nb_dev, 0x31, 0);
604 /* Disable external GFX and enable internal GFX. */
605 l_dword = pci_read_config32(nb_dev, 0x8c);
608 pci_write_config32(nb_dev, 0x8c, l_dword);
610 /* NB_SetDefaultIndexes */
611 pci_write_config32(nb_dev, 0x94, 0x7f);
612 pci_write_config32(nb_dev, 0x60, 0x7f);
613 pci_write_config32(nb_dev, 0xe0, 0);
615 /* NB_InitEarlyNB finished. */
617 /* LPC DMA Deadlock workaround? */
619 device_t k8_f0 = dev_find_slot(0, PCI_DEVFN(0x18, 0));
620 l_dword = pci_read_config32(k8_f0, 0x68);
621 l_dword &= ~(3 << 21);
622 l_dword |= (1 << 21);
623 pci_write_config32(k8_f0, 0x68, l_dword);
625 /* GFX_InitCommon. */
626 nbmc_write_index(nb_dev, 0x23, 0x00c00010);
627 set_nbmc_enable_bits(nb_dev, 0x16, 1<<15, 1<<15);
628 set_nbmc_enable_bits(nb_dev, 0x25, 0xffffffff, 0x111f111f);
629 set_htiu_enable_bits(nb_dev, 0x37, 1<<24, 1<<24);
631 #if (CONFIG_GFXUMA == 1)
633 /* Copy CPU DDR Controller to NB MC. */
634 device_t k8_f2 = dev_find_slot(0, PCI_DEVFN(0x18, 2));
635 for (i = 0; i < 12; i++)
637 l_dword = pci_read_config32(k8_f2, 0x40 + i * 4);
638 nbmc_write_index(nb_dev, 0x30 + i, l_dword);
641 l_dword = pci_read_config32(k8_f2, 0x80);
642 nbmc_write_index(nb_dev, 0x3c, l_dword);
644 l_dword = pci_read_config32(k8_f2, 0x94);
645 if(l_dword & (1<<22))
646 set_nbmc_enable_bits(nb_dev, 0x3c, 0, 1<<16);
648 set_nbmc_enable_bits(nb_dev, 0x3c, 1<<16, 0);
651 set_nbmc_enable_bits(nb_dev, 0x3c, 0, 1<<17);
653 set_nbmc_enable_bits(nb_dev, 0x3c, 1<<17, 0);
655 l_dword = pci_read_config32(k8_f2, 0x90);
656 if(l_dword & (1<<10))
657 set_nbmc_enable_bits(nb_dev, 0x3c, 0, 1<<18);
659 set_nbmc_enable_bits(nb_dev, 0x3c, 1<<18, 0);
661 /* Set UMA in the 780 side. */
662 /* UMA start address, size. */
663 /* The UMA starts at 0xC0000000 of internal RS780 address space
664 [31:16] addr of last byte | [31:16] addr of first byte
666 nbmc_write_index(nb_dev, 0x10, ((uma_memory_size - 1 + 0xC0000000) & (~0xffff)) | 0xc000);
667 nbmc_write_index(nb_dev, 0x11, uma_memory_base);
668 nbmc_write_index(nb_dev, 0x12, 0);
669 nbmc_write_index(nb_dev, 0xf0, 256);
670 /* GFX_InitUMA finished. */
673 /* SP memory:Hynix HY5TQ1G631ZNFP. 128MB = 64M * 16. 667MHz. DDR3. */
675 /* Enable Async mode. */
676 set_nbmc_enable_bits(nb_dev, 0x06, 7<<8, 1<<8);
677 set_nbmc_enable_bits(nb_dev, 0x08, 1<<10, 0);
678 /* The last item in AsynchMclkTaskFileIndex. Why? */
679 /* MC_MPLL_CONTROL2. */
680 nbmc_write_index(nb_dev, 0x07, 0x40100028);
681 /* MC_MPLL_DIV_CONTROL. */
682 nbmc_write_index(nb_dev, 0x0b, 0x00000028);
683 /* MC_MPLL_FREQ_CONTROL. */
684 set_nbmc_enable_bits(nb_dev, 0x09, 3<<12|15<<16|15<<8, 1<<12|4<<16|0<<8);
685 /* MC_MPLL_CONTROL3. For PM. */
686 set_nbmc_enable_bits(nb_dev, 0x08, 0xff<<13, 1<<13|1<<18);
687 /* MPLL_CAL_TRIGGER. */
688 set_nbmc_enable_bits(nb_dev, 0x06, 0, 1<<0);
689 udelay(200); /* time is long enough? */
690 set_nbmc_enable_bits(nb_dev, 0x06, 0, 1<<1);
691 set_nbmc_enable_bits(nb_dev, 0x06, 1<<0, 0);
692 /* MCLK_SRC_USE_MPLL. */
693 set_nbmc_enable_bits(nb_dev, 0x02, 0, 1<<20);
696 nbmc_write_index(nb_dev, 0x01, 0x88108280);
697 set_nbmc_enable_bits(nb_dev, 0x02, ~(1<<20), 0x00030200);
698 nbmc_write_index(nb_dev, 0x04, 0x08881018);
699 nbmc_write_index(nb_dev, 0x05, 0x000000bb);
700 nbmc_write_index(nb_dev, 0x0c, 0x0f00001f);
701 nbmc_write_index(nb_dev, 0xa1, 0x01f10000);
702 /* MCA_INIT_DLL_PM. */
703 set_nbmc_enable_bits(nb_dev, 0xc9, 1<<24, 1<<24);
704 nbmc_write_index(nb_dev, 0xa2, 0x74f20000);
705 nbmc_write_index(nb_dev, 0xa3, 0x8af30000);
706 nbmc_write_index(nb_dev, 0xaf, 0x47d0a41c);
707 nbmc_write_index(nb_dev, 0xb0, 0x88800130);
708 nbmc_write_index(nb_dev, 0xb1, 0x00000040);
709 nbmc_write_index(nb_dev, 0xb4, 0x41247000);
710 nbmc_write_index(nb_dev, 0xb5, 0x00066664);
711 nbmc_write_index(nb_dev, 0xb6, 0x00000022);
712 nbmc_write_index(nb_dev, 0xb7, 0x00000044);
713 nbmc_write_index(nb_dev, 0xb8, 0xbbbbbbbb);
714 nbmc_write_index(nb_dev, 0xb9, 0xbbbbbbbb);
715 nbmc_write_index(nb_dev, 0xba, 0x55555555);
716 nbmc_write_index(nb_dev, 0xc1, 0x00000000);
717 nbmc_write_index(nb_dev, 0xc2, 0x00000000);
718 nbmc_write_index(nb_dev, 0xc3, 0x80006b00);
719 nbmc_write_index(nb_dev, 0xc4, 0x00066664);
720 nbmc_write_index(nb_dev, 0xc5, 0x00000000);
721 nbmc_write_index(nb_dev, 0xd2, 0x00000022);
722 nbmc_write_index(nb_dev, 0xd3, 0x00000044);
723 nbmc_write_index(nb_dev, 0xd6, 0x00050005);
724 nbmc_write_index(nb_dev, 0xd7, 0x00000000);
725 nbmc_write_index(nb_dev, 0xd8, 0x00700070);
726 nbmc_write_index(nb_dev, 0xd9, 0x00700070);
727 nbmc_write_index(nb_dev, 0xe0, 0x00200020);
728 nbmc_write_index(nb_dev, 0xe1, 0x00200020);
729 nbmc_write_index(nb_dev, 0xe8, 0x00200020);
730 nbmc_write_index(nb_dev, 0xe9, 0x00200020);
731 nbmc_write_index(nb_dev, 0xe0, 0x00180018);
732 nbmc_write_index(nb_dev, 0xe1, 0x00180018);
733 nbmc_write_index(nb_dev, 0xe8, 0x00180018);
734 nbmc_write_index(nb_dev, 0xe9, 0x00180018);
737 /* Memory Termination. */
738 set_nbmc_enable_bits(nb_dev, 0xa1, 0x0ff, 0x044);
739 set_nbmc_enable_bits(nb_dev, 0xb4, 0xf00, 0xb00);
741 /* Controller Termation. */
742 set_nbmc_enable_bits(nb_dev, 0xb1, 0x77770000, 0x77770000);
745 /* OEM Init MC. 667MHz. */
746 nbmc_write_index(nb_dev, 0xa8, 0x7a5aaa78);
747 nbmc_write_index(nb_dev, 0xa9, 0x514a2319);
748 nbmc_write_index(nb_dev, 0xaa, 0x54400520);
749 nbmc_write_index(nb_dev, 0xab, 0x441460ff);
750 nbmc_write_index(nb_dev, 0xa0, 0x20f00a48);
751 set_nbmc_enable_bits(nb_dev, 0xa2, ~(0xffffffc7), 0x10);
752 nbmc_write_index(nb_dev, 0xb2, 0x00000303);
753 set_nbmc_enable_bits(nb_dev, 0xb1, ~(0xffffff70), 0x45);
755 /* set_nbmc_enable_bits(nb_dev, 0xac, ~(0xfffffff0), 0x0b); */
757 /* Init PM timing. */
760 l_dword = nbmc_read_index(nb_dev, 0xa0+i);
761 nbmc_write_index(nb_dev, 0xc8+i, l_dword);
765 l_dword = nbmc_read_index(nb_dev, 0xa8+i);
766 nbmc_write_index(nb_dev, 0xcc+i, l_dword);
768 l_dword = nbmc_read_index(nb_dev, 0xb1);
769 set_nbmc_enable_bits(nb_dev, 0xc8, 0xff<<24, ((l_dword&0x0f)<<24)|((l_dword&0xf00)<<20));
772 /* FB_Start = ; FB_End = ; iSpSize = 0x0080, 128MB. */
773 nbmc_write_index(nb_dev, 0x11, 0x40000000);
774 FB_Start = 0xc00 + 0x080;
775 FB_End = 0xc00 + 0x080;
776 nbmc_write_index(nb_dev, 0x10, (((FB_End&0xfff)<<20)-0x10000)|(((FB_Start&0xfff)-0x080)<<4));
777 set_nbmc_enable_bits(nb_dev, 0x0d, ~0x000ffff0, (FB_Start&0xfff)<<20);
778 nbmc_write_index(nb_dev, 0x0f, 0);
779 nbmc_write_index(nb_dev, 0x0e, (FB_Start&0xfff)|(0xaaaa<<12));
782 /* GFX_InitSP finished. */
785 static struct pci_operations lops_pci = {
786 .set_subsystem = pci_dev_set_subsystem,
789 static struct device_operations pcie_ops = {
790 .read_resources = rs780_gfx_read_resources,
791 .set_resources = pci_dev_set_resources,
792 .enable_resources = pci_dev_enable_resources,
793 .init = internal_gfx_pci_dev_init, /* The option ROM initializes the device. rs780_gfx_init, */
795 .enable = rs780_internal_gfx_enable,
796 .ops_pci = &lops_pci,
800 * We should list all of them here.
802 static const struct pci_driver pcie_driver_780 __pci_driver = {
804 .vendor = PCI_VENDOR_ID_ATI,
805 .device = PCI_DEVICE_ID_ATI_RS780_INT_GFX,
808 static const struct pci_driver pcie_driver_780c __pci_driver = {
810 .vendor = PCI_VENDOR_ID_ATI,
811 .device = PCI_DEVICE_ID_ATI_RS780C_INT_GFX,
813 static const struct pci_driver pcie_driver_780m __pci_driver = {
815 .vendor = PCI_VENDOR_ID_ATI,
816 .device = PCI_DEVICE_ID_ATI_RS780M_INT_GFX,
818 static const struct pci_driver pcie_driver_780mc __pci_driver = {
820 .vendor = PCI_VENDOR_ID_ATI,
821 .device = PCI_DEVICE_ID_ATI_RS780MC_INT_GFX,
823 static const struct pci_driver pcie_driver_780e __pci_driver = {
825 .vendor = PCI_VENDOR_ID_ATI,
826 .device = PCI_DEVICE_ID_ATI_RS780E_INT_GFX,
828 static const struct pci_driver pcie_driver_785g __pci_driver = {
830 .vendor = PCI_VENDOR_ID_ATI,
831 .device = PCI_DEVICE_ID_ATI_RS785G_INT_GFX,
834 /* step 12 ~ step 14 from rpr */
835 static void single_port_configuration(device_t nb_dev, device_t dev)
839 struct southbridge_amd_rs780_config *cfg =
840 (struct southbridge_amd_rs780_config *)nb_dev->chip_info;
842 printk(BIOS_DEBUG, "rs780_gfx_init single_port_configuration.\n");
844 /* step 12 training, releases hold training for GFX port 0 (device 2) */
845 PcieReleasePortTraining(nb_dev, dev, 2);
846 result = PcieTrainPort(nb_dev, dev, 2);
847 printk(BIOS_DEBUG, "rs780_gfx_init single_port_configuration step12.\n");
849 /* step 13 Power Down Control */
850 /* step 13.1 Enables powering down transmitter and receiver pads along with PLL macros. */
851 set_pcie_enable_bits(nb_dev, 0x40, 1 << 0, 1 << 0);
853 /* step 13.a Link Training was NOT successful */
855 set_nbmisc_enable_bits(nb_dev, 0x8, 0, 0x3 << 4); /* prevent from training. */
856 set_nbmisc_enable_bits(nb_dev, 0xc, 0, 0x3 << 2); /* hide the GFX bridge. */
858 nbpcie_ind_write_index(nb_dev, 0x65, 0xccf0f0);
860 nbpcie_ind_write_index(nb_dev, 0x65, 0xffffffff);
861 set_nbmisc_enable_bits(nb_dev, 0x7, 1 << 3, 1 << 3);
863 } else { /* step 13.b Link Training was successful */
864 set_pcie_enable_bits(dev, 0xA2, 0xFF, 0x1);
865 reg32 = nbpcie_p_read_index(dev, 0x29);
866 width = reg32 & 0xFF;
867 printk(BIOS_DEBUG, "GFX Inactive Lanes = 0x%x.\n", width);
871 nbpcie_ind_write_index(nb_dev, 0x65,
872 cfg->gfx_lane_reversal ? 0x7f7f : 0xccfefe);
875 nbpcie_ind_write_index(nb_dev, 0x65,
876 cfg->gfx_lane_reversal ? 0x3f3f : 0xccfcfc);
879 nbpcie_ind_write_index(nb_dev, 0x65,
880 cfg->gfx_lane_reversal ? 0x0f0f : 0xccf0f0);
884 printk(BIOS_DEBUG, "rs780_gfx_init single_port_configuration step13.\n");
886 /* step 14 Reset Enumeration Timer, disables the shortening of the enumeration timer */
887 set_pcie_enable_bits(dev, 0x70, 1 << 19, 1 << 19);
888 printk(BIOS_DEBUG, "rs780_gfx_init single_port_configuration step14.\n");
891 static void dual_port_configuration(device_t nb_dev, device_t dev)
894 u32 reg32, dev_ind = dev->path.pci.devfn >> 3;
895 struct southbridge_amd_rs780_config *cfg =
896 (struct southbridge_amd_rs780_config *)nb_dev->chip_info;
898 /* 5.4.1.2 Dual Port Configuration */
899 set_nbmisc_enable_bits(nb_dev, 0x36, 1 << 31, 1 << 31);
900 set_nbmisc_enable_bits(nb_dev, 0x08, 0xF << 8, 0x5 << 8);
901 set_nbmisc_enable_bits(nb_dev, 0x36, 1 << 31, 0 << 31);
903 /* 5.7. Training for Device 2 */
904 /* 5.7.1. Releases hold training for GFX port 0 (device 2) */
905 PcieReleasePortTraining(nb_dev, dev, dev_ind);
906 /* 5.7.2- 5.7.9. PCIE Link Training Sequence */
907 result = PcieTrainPort(nb_dev, dev, dev_ind);
909 /* Power Down Control for Device 2 */
910 /* Link Training was NOT successful */
912 /* Powers down all lanes for port A */
913 /* nbpcie_ind_write_index(nb_dev, 0x65, 0x0f0f); */
914 /* Note: I have to disable the slot where there isnt a device,
915 * otherwise the system will hang. I dont know why. */
916 set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << dev_ind, 1 << dev_ind);
918 } else { /* step 16.b Link Training was successful */
919 reg32 = nbpcie_p_read_index(dev, 0xa2);
920 width = (reg32 >> 4) & 0x7;
921 printk(BIOS_DEBUG, "GFX LC_LINK_WIDTH = 0x%x.\n", width);
925 nbpcie_ind_write_index(nb_dev, 0x65,
926 cfg->gfx_lane_reversal ? 0x0707 : 0x0e0e);
929 nbpcie_ind_write_index(nb_dev, 0x65,
930 cfg->gfx_lane_reversal ? 0x0303 : 0x0c0c);
936 /* For single port GFX configuration Only
943 * 101 = x12 (not supported)
946 static void dynamic_link_width_control(device_t nb_dev, device_t dev, u8 width)
950 struct southbridge_amd_rs780_config *cfg =
951 (struct southbridge_amd_rs780_config *)nb_dev->chip_info;
954 reg32 = nbpcie_p_read_index(dev, 0xa2);
957 set_pcie_enable_bits(nb_dev, 0x40, 1 << 0, 1 << 0);
959 set_pcie_enable_bits(dev, 0xa2, 3 << 0, width << 0);
961 set_pcie_enable_bits(dev, 0xa2, 1 << 8, 1 << 8);
963 if (0 == cfg->gfx_reconfiguration)
964 set_pcie_enable_bits(dev, 0xa2, 1 << 11, 1 << 11);
968 reg32 = nbpcie_p_read_index(dev, 0xa2);
970 while (reg32 & 0x100);
973 sb_dev = dev_find_slot(0, PCI_DEVFN(8, 0));
975 reg32 = pci_ext_read_config32(nb_dev, sb_dev,
976 PCIE_VC0_RESOURCE_STATUS);
977 } while (reg32 & VC_NEGOTIATION_PENDING);
980 reg32 = nbpcie_p_read_index(dev, 0xa2);
981 if (((reg32 & 0x70) >> 4) != 0x6) {
982 /* the unused lanes should be powered off. */
986 set_pcie_enable_bits(nb_dev, 0x40, 1 << 0, 0 << 0);
990 * GFX Core initialization, dev2, dev3
992 void rs780_gfx_init(device_t nb_dev, device_t dev, u32 port)
995 struct southbridge_amd_rs780_config *cfg =
996 (struct southbridge_amd_rs780_config *)nb_dev->chip_info;
998 printk(BIOS_DEBUG, "rs780_gfx_init, nb_dev=0x%p, dev=0x%p, port=0x%x.\n",
1001 /* GFX Core Initialization */
1002 //if (port == 2) return;
1004 /* step 2, TMDS, (only need if CMOS option is enabled) */
1005 if (cfg->gfx_tmds) {
1008 #if 1 /* external clock mode */
1009 /* table 5-22, 5.9.1. REFCLK */
1010 /* 5.9.1.1. Disables the GFX REFCLK transmitter so that the GFX
1011 * REFCLK PAD can be driven by an external source. */
1012 /* 5.9.1.2. Enables GFX REFCLK receiver to receive the REFCLK from an external source. */
1013 set_nbmisc_enable_bits(nb_dev, 0x38, 1 << 29 | 1 << 28, 0 << 29 | 1 << 28);
1015 /* 5.9.1.3 Selects the GFX REFCLK to be the source for PLL A. */
1016 /* 5.9.1.4 Selects the GFX REFCLK to be the source for PLL B. */
1017 /* 5.9.1.5 Selects the GFX REFCLK to be the source for PLL C. */
1018 set_nbmisc_enable_bits(nb_dev, 0x28, 3 << 6 | 3 << 8 | 3 << 10,
1019 1 << 6 | 1 << 8 | 1 << 10);
1020 reg32 = nbmisc_read_index(nb_dev, 0x28);
1021 printk(BIOS_DEBUG, "misc 28 = %x\n", reg32);
1023 /* 5.9.1.6.Selects the single ended GFX REFCLK to be the source for core logic. */
1024 set_nbmisc_enable_bits(nb_dev, 0x6C, 1 << 31, 1 << 31);
1025 #else /* internal clock mode */
1026 /* table 5-23, 5.9.1. REFCLK */
1027 /* 5.9.1.1. Enables the GFX REFCLK transmitter so that the GFX
1028 * REFCLK PAD can be driven by the SB REFCLK. */
1029 /* 5.9.1.2. Disables GFX REFCLK receiver from receiving the
1030 * REFCLK from an external source.*/
1031 set_nbmisc_enable_bits(nb_dev, 0x38, 1 << 29 | 1 << 28, 1 << 29 | 0 << 28);
1033 /* 5.9.1.3 Selects the GFX REFCLK to be the source for PLL A. */
1034 /* 5.9.1.4 Selects the GFX REFCLK to be the source for PLL B. */
1035 /* 5.9.1.5 Selects the GFX REFCLK to be the source for PLL C. */
1036 set_nbmisc_enable_bits(nb_dev, 0x28, 3 << 6 | 3 << 8 | 3 << 10,
1038 reg32 = nbmisc_read_index(nb_dev, 0x28);
1039 printk(BIOS_DEBUG, "misc 28 = %x\n", reg32);
1041 /* 5.9.1.6.Selects the single ended GFX REFCLK to be the source for core logic. */
1042 set_nbmisc_enable_bits(nb_dev, 0x6C, 1 << 31, 0 << 31);
1045 /* step 5.9.3, GFX overclocking, (only need if CMOS option is enabled) */
1046 /* 5.9.3.1. Increases PLL BW for 6G operation.*/
1047 /* set_nbmisc_enable_bits(nb_dev, 0x36, 0x3FF << 4, 0xB5 << 4); */
1050 /* step 5.9.4, reset the GFX link */
1051 /* step 5.9.4.1 asserts both calibration reset and global reset */
1052 set_nbmisc_enable_bits(nb_dev, 0x8, 0x3 << 14, 0x3 << 14);
1054 /* step 5.9.4.2 de-asserts calibration reset */
1055 set_nbmisc_enable_bits(nb_dev, 0x8, 1 << 14, 0 << 14);
1057 /* step 5.9.4.3 wait for at least 200us */
1060 /* step 5.9.4.4 de-asserts global reset */
1061 set_nbmisc_enable_bits(nb_dev, 0x8, 1 << 15, 0 << 15);
1063 /* 5.9.5 Reset PCIE_GFX Slot */
1064 /* It is done in mainboard.c */
1069 /* step 5.9.8 program PCIE memory mapped configuration space */
1070 /* done by enable_pci_bar3() before */
1072 /* step 7 compliance state, (only need if CMOS option is enabled) */
1073 /* the compliance stete is just for test. refer to 4.2.5.2 of PCIe specification */
1074 if (cfg->gfx_compliance) {
1075 /* force compliance */
1076 set_nbmisc_enable_bits(nb_dev, 0x32, 1 << 6, 1 << 6);
1077 /* release hold training for device 2. GFX initialization is done. */
1078 set_nbmisc_enable_bits(nb_dev, 0x8, 1 << 4, 0 << 4);
1079 dynamic_link_width_control(nb_dev, dev, cfg->gfx_link_width);
1080 printk(BIOS_DEBUG, "rs780_gfx_init step7.\n");
1084 /* 5.9.12 Core Initialization. */
1085 /* 5.9.12.1 sets RCB timeout to be 25ms */
1086 /* 5.9.12.2. RCB Cpl timeout on link down. */
1087 set_pcie_enable_bits(dev, 0x70, 7 << 16 | 1 << 19, 4 << 16 | 1 << 19);
1088 printk(BIOS_DEBUG, "rs780_gfx_init step5.9.12.1.\n");
1090 /* step 5.9.12.3 disables slave ordering logic */
1091 set_pcie_enable_bits(nb_dev, 0x20, 1 << 8, 1 << 8);
1092 printk(BIOS_DEBUG, "rs780_gfx_init step5.9.12.3.\n");
1094 /* step 5.9.12.4 sets DMA payload size to 64 bytes */
1095 set_pcie_enable_bits(nb_dev, 0x10, 7 << 10, 4 << 10);
1096 /* 5.9.12.5. Blocks DMA traffic during C3 state. */
1097 set_pcie_enable_bits(dev, 0x10, 1 << 0, 0 << 0);
1099 /* 5.9.12.6. Disables RC ordering logic */
1100 set_pcie_enable_bits(nb_dev, 0x20, 1 << 9, 1 << 9);
1102 /* Enabels TLP flushing. */
1103 /* Note: It is got from RS690. The system will hang without this action. */
1104 set_pcie_enable_bits(dev, 0x20, 1 << 19, 0 << 19);
1106 /* 5.9.12.7. Ignores DLLPs during L1 so that txclk can be turned off */
1107 set_pcie_enable_bits(nb_dev, 0x2, 1 << 0, 1 << 0);
1109 /* 5.9.12.8 Prevents LC to go from L0 to Rcv_L0s if L1 is armed. */
1110 set_pcie_enable_bits(dev, 0xA1, 1 << 11, 1 << 11);
1112 /* 5.9.12.9 CMGOOD_OVERRIDE for end point initiated lane degradation. */
1113 set_nbmisc_enable_bits(nb_dev, 0x6a, 1 << 17, 1 << 17);
1114 printk(BIOS_DEBUG, "rs780_gfx_init step5.9.12.9.\n");
1116 /* 5.9.12.10 Sets the timer in Config state from 20us to */
1117 /* 5.9.12.11 De-asserts RX_EN in L0s. */
1118 /* 5.9.12.12 Enables de-assertion of PG2RX_CR_EN to lock clock
1119 * recovery parameter when lane is in electrical idle in L0s.*/
1120 set_pcie_enable_bits(dev, 0xB1, 1 << 23 | 1 << 19 | 1 << 28, 1 << 23 | 1 << 19 | 1 << 28);
1122 /* 5.9.12.13. Turns off offset calibration. */
1123 /* 5.9.12.14. Enables Rx Clock gating in CDR */
1124 set_nbmisc_enable_bits(nb_dev, 0x34, 1 << 10/* | 1 << 22 */, 1 << 10/* | 1 << 22 */);
1126 /* 5.9.12.15. Sets number of TX Clocks to drain TX Pipe to 3. */
1127 set_pcie_enable_bits(dev, 0xA0, 0xF << 4, 3 << 4);
1129 /* 5.9.12.16. Lets PI use Electrical Idle from PHY when
1130 * turning off PLL in L1 at Gen2 speed instead Inferred Electrical Idle. */
1131 set_pcie_enable_bits(nb_dev, 0x40, 3 << 14, 2 << 14);
1133 /* 5.9.12.17. Prevents the Electrical Idle from causing a transition from Rcv_L0 to Rcv_L0s. */
1134 set_pcie_enable_bits(dev, 0xB1, 1 << 20, 1 << 20);
1136 /* 5.9.12.18. Prevents the LTSSM from going to Rcv_L0s if it has already
1137 * acknowledged a request to go to L1. */
1138 set_pcie_enable_bits(dev, 0xA1, 1 << 11, 1 << 11);
1140 /* 5.9.12.19. LDSK only taking deskew on deskewing error detect */
1141 set_pcie_enable_bits(nb_dev, 0x40, 1 << 28, 0 << 28);
1143 /* 5.9.12.20. Bypasses lane de-skew logic if in x1 */
1144 set_pcie_enable_bits(nb_dev, 0xC2, 1 << 14, 1 << 14);
1146 /* 5.9.12.21. Sets Electrical Idle Threshold. */
1147 set_nbmisc_enable_bits(nb_dev, 0x35, 3 << 21, 2 << 21);
1149 /* 5.9.12.22. Advertises -6 dB de-emphasis value in TS1 Data Rate Identifier
1150 * Only if CMOS Option in section. skip */
1152 /* 5.9.12.23. Disables GEN2 capability of the device. */
1153 set_pcie_enable_bits(dev, 0xA4, 1 << 0, 0 << 0);
1155 /* 5.9.12.24.Disables advertising Upconfigure Support. */
1156 set_pcie_enable_bits(dev, 0xA2, 1 << 13, 1 << 13);
1158 /* 5.9.12.25. No comment in RPR. */
1159 set_nbmisc_enable_bits(nb_dev, 0x39, 1 << 10, 0 << 10);
1161 /* 5.9.12.26. This capacity is required since links wider than x1 and/or multiple link
1162 * speed are supported */
1163 set_pcie_enable_bits(nb_dev, 0xC1, 1 << 0, 1 << 0);
1165 /* 5.9.12.27. Enables NVG86 ECO. A13 above only. */
1166 if (get_nb_rev(nb_dev) == REV_RS780_A12) /* A12 */
1167 set_pcie_enable_bits(dev, 0x02, 1 << 11, 1 << 11);
1169 /* 5.9.12.28 Hides and disables the completion timeout method. */
1170 set_pcie_enable_bits(nb_dev, 0xC1, 1 << 2, 0 << 2);
1172 /* 5.9.12.29. Use the bif_core de-emphasis strength by default. */
1173 /* set_nbmisc_enable_bits(nb_dev, 0x36, 1 << 28, 1 << 28); */
1175 /* 5.9.12.30. Set TX arbitration algorithm to round robin */
1176 set_pcie_enable_bits(nb_dev, 0x1C,
1177 1 << 0 | 0x1F << 1 | 0x1F << 6,
1178 1 << 0 | 0x04 << 1 | 0x04 << 6);
1180 /* Single-port/Dual-port configureation. */
1181 switch (cfg->gfx_dual_slot) {
1183 /* step 1, lane reversal (only need if build config option is enabled) */
1184 if (cfg->gfx_lane_reversal) {
1185 set_nbmisc_enable_bits(nb_dev, 0x36, 1 << 31, 1 << 31);
1186 set_nbmisc_enable_bits(nb_dev, 0x33, 1 << 2, 1 << 2);
1187 set_nbmisc_enable_bits(nb_dev, 0x36, 1 << 31, 0 << 31);
1189 printk(BIOS_DEBUG, "rs780_gfx_init step1.\n");
1191 printk(BIOS_DEBUG, "device = %x\n", dev->path.pci.devfn >> 3);
1192 if((dev->path.pci.devfn >> 3) == 2) {
1193 single_port_configuration(nb_dev, dev);
1195 set_nbmisc_enable_bits(nb_dev, 0xc, 0, 0x2 << 2); /* hide the GFX bridge. */
1196 printk(BIOS_INFO, "Single port. Do nothing.\n"); // If dev3
1201 /* step 1, lane reversal (only need if build config option is enabled) */
1202 if (cfg->gfx_lane_reversal) {
1203 set_nbmisc_enable_bits(nb_dev, 0x36, 1 << 31, 1 << 31);
1204 set_nbmisc_enable_bits(nb_dev, 0x33, 1 << 2, 1 << 2);
1205 set_nbmisc_enable_bits(nb_dev, 0x33, 1 << 3, 1 << 3);
1206 set_nbmisc_enable_bits(nb_dev, 0x36, 1 << 31, 0 << 31);
1208 printk(BIOS_DEBUG, "rs780_gfx_init step1.\n");
1209 /* step 1.1, dual-slot gfx configuration (only need if CMOS option is enabled) */
1210 /* AMD calls the configuration CrossFire */
1211 set_nbmisc_enable_bits(nb_dev, 0x0, 0xf << 8, 5 << 8);
1212 printk(BIOS_DEBUG, "rs780_gfx_init step2.\n");
1214 printk(BIOS_DEBUG, "device = %x\n", dev->path.pci.devfn >> 3);
1215 dual_port_configuration(nb_dev, dev);
1220 if(is_dev3_present()){
1221 /* step 1, lane reversal (only need if CMOS option is enabled) */
1222 if (cfg->gfx_lane_reversal) {
1223 set_nbmisc_enable_bits(nb_dev, 0x33, 1 << 2, 1 << 2);
1224 set_nbmisc_enable_bits(nb_dev, 0x33, 1 << 3, 1 << 3);
1226 printk(BIOS_DEBUG, "rs780_gfx_init step1.\n");
1227 /* step 1.1, dual-slot gfx configuration (only need if CMOS option is enabled) */
1228 /* AMD calls the configuration CrossFire */
1229 set_nbmisc_enable_bits(nb_dev, 0x0, 0xf << 8, 5 << 8);
1230 printk(BIOS_DEBUG, "rs780_gfx_init step2.\n");
1233 printk(BIOS_DEBUG, "device = %x\n", dev->path.pci.devfn >> 3);
1234 dual_port_configuration(nb_dev, dev);
1237 if (cfg->gfx_lane_reversal) {
1238 set_nbmisc_enable_bits(nb_dev, 0x33, 1 << 2, 1 << 2);
1240 printk(BIOS_DEBUG, "rs780_gfx_init step1.\n");
1241 printk(BIOS_DEBUG, "rs780_gfx_init step2.\n");
1243 if((dev->path.pci.devfn >> 3) == 2)
1244 single_port_configuration(nb_dev, dev);
1246 set_nbmisc_enable_bits(nb_dev, 0xc, 0, 0x2 << 2); /* hide the GFX bridge. */
1247 printk(BIOS_DEBUG, "If dev3.., single port. Do nothing.\n");
1252 printk(BIOS_INFO, "Incorrect configuration of external GFX slot.\n");