2 * This file is part of the coreboot project.
4 * Copyright (C) 2010 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 #include <console/console.h>
22 #include <device/device.h>
23 #include <device/pci.h>
24 #include <device/pci_ids.h>
25 #include <device/pci_ops.h>
26 #include <cpu/x86/msr.h>
27 #include <cpu/amd/mtrr.h>
30 /*****************************************
31 * rs780_config_misc_clk()
32 *****************************************/
33 void static rs780_config_misc_clk(device_t nb_dev)
38 struct bus pbus; /* fake bus for dev0 fun1 */
40 reg = pci_read_config32(nb_dev, 0x4c);
42 pci_write_config32(nb_dev, 0x4c, reg);
44 word = pci_cf8_conf1.read16(&pbus, 0, 1, 0xf8);
46 pci_cf8_conf1.write16(&pbus, 0, 1, 0xf8, word);
48 word = pci_cf8_conf1.read16(&pbus, 0, 1, 0xe8);
49 word &= ~((1 << 12) | (1 << 13) | (1 << 14));
51 pci_cf8_conf1.write16(&pbus, 0, 1, 0xe8, word);
53 reg = pci_cf8_conf1.read32(&pbus, 0, 1, 0x94);
54 reg &= ~((1 << 16) | (1 << 24) | (1 << 28));
55 pci_cf8_conf1.write32(&pbus, 0, 1, 0x94, reg);
57 reg = pci_cf8_conf1.read32(&pbus, 0, 1, 0x8c);
58 reg &= ~((1 << 13) | (1 << 14) | (1 << 24) | (1 << 25));
60 pci_cf8_conf1.write32(&pbus, 0, 1, 0x8c, reg);
62 reg = pci_cf8_conf1.read32(&pbus, 0, 1, 0xcc);
64 pci_cf8_conf1.write32(&pbus, 0, 1, 0xcc, reg);
66 reg = nbmc_read_index(nb_dev, 0x7a);
70 set_htiu_enable_bits(nb_dev, 0x05, 1 << 11, 1 << 11);
71 nbmc_write_index(nb_dev, 0x7a, reg);
72 /* Powering Down efuse and strap block clocks after boot-up. GFX Mode. */
73 reg = pci_cf8_conf1.read32(&pbus, 0, 1, 0xcc);
76 pci_cf8_conf1.write32(&pbus, 0, 1, 0xcc, reg);
78 /* Programming NB CLK table. */
79 byte = pci_cf8_conf1.read8(&pbus, 0, 1, 0xe0);
81 pci_cf8_conf1.write8(&pbus, 0, 1, 0xe0, byte);
84 /* Powerdown reference clock to graphics core PLL in northbridge only mode */
85 reg = pci_cf8_conf1.read32(&pbus, 0, 1, 0x8c);
87 pci_cf8_conf1.write32(&pbus, 0, 1, 0x8c, reg);
89 /* Powering Down efuse and strap block clocks after boot-up. NB Only Mode. */
90 reg = pci_cf8_conf1.read32(&pbus, 0, 1, 0xcc);
91 reg |= (1 << 23) | (1 << 24);
92 pci_cf8_conf1.write32(&pbus, 0, 1, 0xcc, reg);
94 /* Powerdown clock to memory controller in northbridge only mode */
95 byte = pci_cf8_conf1.read8(&pbus, 0, 1, 0xe4);
97 pci_cf8_conf1.write8(&pbus, 0, 1, 0xe4, reg);
99 /* CLKCFG:0xE8 Bit[17] = 0x1 Powerdown clock to IOC GFX block in no external graphics mode */
103 reg = pci_read_config32(nb_dev, 0x4c);
105 pci_write_config32(nb_dev, 0x4c, reg);
107 set_htiu_enable_bits(nb_dev, 0x05, 7 << 8, 7 << 8);
110 u32 get_vid_did(device_t dev)
112 return pci_read_config32(dev, 0);
115 void rs780_nb_pci_table(device_t nb_dev)
116 { /* NBPOR_InitPOR function. */
121 /* Program NB PCI table. */
122 temp16 = pci_read_config16(nb_dev, 0x04);
123 printk(BIOS_DEBUG, "NB_PCI_REG04 = %x.\n", temp16);
124 temp32 = pci_read_config32(nb_dev, 0x84);
125 printk(BIOS_DEBUG, "NB_PCI_REG84 = %x.\n", temp32);
127 pci_write_config8(nb_dev, 0x4c, 0x42);
129 temp8 = pci_read_config8(nb_dev, 0x4e);
131 pci_write_config8(nb_dev, 0x4e, temp8);
133 temp32 = pci_read_config32(nb_dev, 0x4c);
134 printk(BIOS_DEBUG, "NB_PCI_REG4C = %x.\n", temp32);
136 /* disable GFX debug. */
137 temp8 = pci_read_config8(nb_dev, 0x8d);
139 pci_write_config8(nb_dev, 0x8d, temp8);
141 /* set temporary NB TOM to 0x40000000. */
142 rs780_set_tom(nb_dev);
144 /* Program NB HTIU table. */
146 set_htiu_enable_bits(nb_dev, 0x05, 1<<10 | 1<<9, 1<<10|1<<9);
147 set_htiu_enable_bits(nb_dev, 0x06, 1, 0x4203a202);
148 set_htiu_enable_bits(nb_dev, 0x07, 1<<1 | 1<<2, 0x8001);
149 set_htiu_enable_bits(nb_dev, 0x15, 0, 1<<31 | 1<<30 | 1<<27);
150 set_htiu_enable_bits(nb_dev, 0x1c, 0, 0xfffe0000);
151 set_htiu_enable_bits(nb_dev, 0x4b, 1<<11, 1<<11);
152 set_htiu_enable_bits(nb_dev, 0x0c, 0x3f, 1 | 1<<3);
153 set_htiu_enable_bits(nb_dev, 0x17, 1<<1 | 1<<27, 1<<1);
154 set_htiu_enable_bits(nb_dev, 0x17, 0, 1<<30);
155 set_htiu_enable_bits(nb_dev, 0x19, 0xfffff+(1<<31), 0x186a0+(1<<31));
156 set_htiu_enable_bits(nb_dev, 0x16, 0x3f<<10, 0x7<<10);
157 set_htiu_enable_bits(nb_dev, 0x23, 0, 1<<28);
159 /* Program NB MISC table. */
160 set_nbmisc_enable_bits(nb_dev, 0x0b, 0xffff, 0x00000180);
161 set_nbmisc_enable_bits(nb_dev, 0x00, 0xffff, 0x00000106);
162 set_nbmisc_enable_bits(nb_dev, 0x51, 0xffffffff, 0x00100100);
163 set_nbmisc_enable_bits(nb_dev, 0x53, 0xffffffff, 0x00100100);
164 set_nbmisc_enable_bits(nb_dev, 0x55, 0xffffffff, 0x00100100);
165 set_nbmisc_enable_bits(nb_dev, 0x57, 0xffffffff, 0x00100100);
166 set_nbmisc_enable_bits(nb_dev, 0x59, 0xffffffff, 0x00100100);
167 set_nbmisc_enable_bits(nb_dev, 0x5b, 0xffffffff, 0x00100100);
168 set_nbmisc_enable_bits(nb_dev, 0x5d, 0xffffffff, 0x00100100);
169 set_nbmisc_enable_bits(nb_dev, 0x5f, 0xffffffff, 0x00100100);
170 set_nbmisc_enable_bits(nb_dev, 0x20, 1<<1, 0);
171 set_nbmisc_enable_bits(nb_dev, 0x37, 1<<11|1<<12|1<<13|1<<26, 0);
172 set_nbmisc_enable_bits(nb_dev, 0x68, 1<<5|1<<6, 1<<5);
173 set_nbmisc_enable_bits(nb_dev, 0x6b, 1<<22, 1<<10);
174 set_nbmisc_enable_bits(nb_dev, 0x67, 1<<26, 1<<14|1<<10);
175 set_nbmisc_enable_bits(nb_dev, 0x24, 1<<28|1<<26|1<<25|1<<16, 1<<29|1<<25);
176 set_nbmisc_enable_bits(nb_dev, 0x38, 1<<24|1<<25, 1<<24);
177 set_nbmisc_enable_bits(nb_dev, 0x36, 1<<29, 1<<29|1<<28);
178 set_nbmisc_enable_bits(nb_dev, 0x0c, 0, 1<<13);
179 set_nbmisc_enable_bits(nb_dev, 0x34, 1<<22, 1<<10);
180 set_nbmisc_enable_bits(nb_dev, 0x39, 1<<10, 1<<30);
181 set_nbmisc_enable_bits(nb_dev, 0x22, 1<<3, 0);
182 set_nbmisc_enable_bits(nb_dev, 0x68, 1<<19, 0);
183 set_nbmisc_enable_bits(nb_dev, 0x24, 1<<16|1<<17, 1<<17);
184 set_nbmisc_enable_bits(nb_dev, 0x6a, 1<<22|1<<23, 1<<17|1<<23);
185 set_nbmisc_enable_bits(nb_dev, 0x35, 1<<21|1<<22, 1<<22);
186 set_nbmisc_enable_bits(nb_dev, 0x01, 0xffffffff, 0x48);
188 /* the last two step. */
189 set_nbmisc_enable_bits(nb_dev, 0x01, 1<<8, 1<<8);
190 set_htiu_enable_bits(nb_dev, 0x2d, 1<<6|1<<4, 1<<6|1<<4);
194 void rs780_nb_gfx_dev_table(device_t nb_dev, device_t dev)
196 /* NB_InitGFXStraps */
197 u32 MMIOBase, apc04, apc18, apc24;
198 volatile u32 * strap;
200 /* Get PCIe configuration space. */
201 MMIOBase = pci_read_config32(nb_dev, 0x1c) & 0xfffffff0;
202 /* Temporarily disable PCIe configuration space. */
203 set_htiu_enable_bits(nb_dev, 0x32, 1<<28, 0);
205 set_nbmisc_enable_bits(nb_dev, 0x1e, 0xffffffff, 1<<1 | 1<<4 | 1<<6 | 1<<7);
206 /* Set a temporary Bus number. */
207 apc18 = pci_read_config32(dev, 0x18);
208 pci_write_config32(dev, 0x18, 0x010100);
209 /* Set MMIO for AGP target(graphics controller). base = 0xe0000000, limit = 0x20000 */
210 apc24 = pci_read_config32(dev, 0x24);
211 pci_write_config32(dev, 0x24, (MMIOBase>>16)+((MMIOBase+0x20000)&0xffff0000));
212 /* Enable memory access. */
213 apc04 = pci_read_config32(dev, 0x04);
214 pci_write_config8(dev, 0x04, 0x02);
216 /* Program Straps. */
217 strap = MMIOBase + 0x15020;
218 #if (CONFIG_GFXUMA == 1)
219 *strap = 1<<7; /* the format of BIF_MEM_AP_SIZE. 001->256MB? */
221 *strap = 0; /* 128M SP memory, 000 -> 128MB */
223 strap = MMIOBase + 0x15000;
225 strap = MMIOBase + 0x15010;
227 //strap = MMIOBase + 0x15020;
228 //*strap |= 0x00000040; /* Disable HDA device. */
229 strap = MMIOBase + 0x15030;
231 strap = MMIOBase + 0x15040;
233 strap = MMIOBase + 0x15050;
235 strap = MMIOBase + 0x15220;
237 strap = MMIOBase + 0x15060;
240 /* BIF switches into normal functional mode. */
241 set_nbmisc_enable_bits(nb_dev, 0x1e, 1<<4 | 1<<5, 1<<5);
243 /* NB Revision is A12. */
244 set_nbmisc_enable_bits(nb_dev, 0x1e, 1<<9, 1<<9);
246 /* Restore APC04, APC18, APC24. */
247 pci_write_config32(dev, 0x04, apc04);
248 pci_write_config32(dev, 0x18, apc18);
249 pci_write_config32(dev, 0x24, apc24);
251 /* Enable PCIe configuration space. */
252 set_htiu_enable_bits(nb_dev, 0x32, 0, 1<<28);
253 printk(BIOS_INFO, "GC is accessible from now on.\n");
256 /***********************************************
258 * 0:00.1 CLK : bit 0 of nb_cfg 0x4c : 0 - disable, default
259 * 0:01.0 P2P Internal:
260 * 0:02.0 P2P : bit 2 of nbmiscind 0x0c : 0 - enable, default + 32 * 2
261 * 0:03.0 P2P : bit 3 of nbmiscind 0x0c : 0 - enable, default + 32 * 2
262 * 0:04.0 P2P : bit 4 of nbmiscind 0x0c : 0 - enable, default + 32 * 2
263 * 0:05.0 P2P : bit 5 of nbmiscind 0x0c : 0 - enable, default + 32 * 2
264 * 0:06.0 P2P : bit 6 of nbmiscind 0x0c : 0 - enable, default + 32 * 2
265 * 0:07.0 P2P : bit 7 of nbmiscind 0x0c : 0 - enable, default + 32 * 2
266 * 0:08.0 NB2SB : bit 6 of nbmiscind 0x00 : 0 - disable, default + 32 * 1
267 * case 0 will be called twice, one is by cpu in hypertransport.c line458,
268 * the other is by rs780.
269 ***********************************************/
270 void rs780_enable(device_t dev)
272 device_t nb_dev = 0, sb_dev = 0;
275 printk(BIOS_INFO, "rs780_enable: dev=%p, VID_DID=0x%x\n", dev, get_vid_did(dev));
277 nb_dev = dev_find_slot(0, PCI_DEVFN(0, 0));
279 die("rs780_enable: CAN NOT FIND RS780 DEVICE, HALT!\n");
283 /* sb_dev (dev 8) is a bridge that links to southbridge. */
284 sb_dev = dev_find_slot(0, PCI_DEVFN(8, 0));
286 die("rs780_enable: CAN NOT FIND SB bridge, HALT!\n");
290 dev_ind = dev->path.pci.devfn >> 3;
292 case 0: /* bus0, dev0, fun0; */
293 printk(BIOS_INFO, "Bus-0, Dev-0, Fun-0.\n");
294 enable_pcie_bar3(nb_dev); /* PCIEMiscInit */
295 config_gpp_core(nb_dev, sb_dev);
296 rs780_gpp_sb_init(nb_dev, sb_dev, 8);
297 /* 5.10.8.4. set SB payload size: 64byte */
298 set_pcie_enable_bits(nb_dev, 0x10 | PCIE_CORE_INDEX_GPPSB, 3 << 11, 2 << 11);
300 /* Bus0Dev0Fun1Clock control init, we have to do it here, for dev0 Fun1 doesn't have a vendor or device ID */
301 rs780_config_misc_clk(nb_dev);
303 rs780_nb_pci_table(nb_dev);
306 case 1: /* bus0, dev1, APC. */
307 printk(BIOS_INFO, "Bus-0, Dev-1, Fun-0.\n");
308 rs780_nb_gfx_dev_table(nb_dev, dev);
310 case 2: /* bus0, dev2,3, two GFX */
312 printk(BIOS_INFO, "Bus-0, Dev-2,3, Fun-0. enable=%d\n", dev->enabled);
313 set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << dev_ind,
314 (dev->enabled ? 0 : 1) << dev_ind);
316 rs780_gfx_init(nb_dev, dev, dev_ind);
318 case 4: /* bus0, dev4-7, four GPPSB */
322 printk(BIOS_INFO, "Bus-0, Dev-4,5,6,7, Fun-0. enable=%d\n",
324 set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << dev_ind,
325 (dev->enabled ? 0 : 1) << dev_ind);
327 rs780_gpp_sb_init(nb_dev, dev, dev_ind);
329 case 8: /* bus0, dev8, SB */
330 printk(BIOS_INFO, "Bus-0, Dev-8, Fun-0. enable=%d\n", dev->enabled);
331 set_nbmisc_enable_bits(nb_dev, 0x00, 1 << 6,
332 (dev->enabled ? 1 : 0) << 6);
334 rs780_gpp_sb_init(nb_dev, dev, dev_ind);
335 disable_pcie_bar3(nb_dev);
337 case 9: /* bus 0, dev 9,10, GPP */
339 printk(BIOS_INFO, "Bus-0, Dev-9, 10, Fun-0. enable=%d\n",
341 enable_pcie_bar3(nb_dev); /* PCIEMiscInit */
342 set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << (7 + dev_ind),
343 (dev->enabled ? 0 : 1) << (7 + dev_ind));
345 rs780_gpp_sb_init(nb_dev, dev, dev_ind);
346 /* Dont call disable_pcie_bar3(nb_dev) here, otherwise the screen will crash. */
349 printk(BIOS_DEBUG, "unknown dev: %s\n", dev_path(dev));
353 struct chip_operations southbridge_amd_rs780_ops = {
354 CHIP_NAME("ATI RS780")
355 .enable_dev = rs780_enable,