2 * This file is part of the coreboot project.
4 * Copyright (C) 2008 Advanced Micro Devices, Inc.
5 * Copyright (C) 2008 Carl-Daniel Hailfinger
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 #define NBHTIU_INDEX 0xA8
23 #define NBMISC_INDEX 0x60
24 #define NBMC_INDEX 0xE8
26 static u32 nb_read_index(device_t dev, u32 index_reg, u32 index)
28 pci_write_config32(dev, index_reg, index);
29 return pci_read_config32(dev, index_reg + 0x4);
32 static void nb_write_index(device_t dev, u32 index_reg, u32 index, u32 data)
34 pci_write_config32(dev, index_reg, index /* | 0x80 */ );
35 pci_write_config32(dev, index_reg + 0x4, data);
38 static u32 nbmisc_read_index(device_t nb_dev, u32 index)
40 return nb_read_index((nb_dev), NBMISC_INDEX, (index));
43 static void nbmisc_write_index(device_t nb_dev, u32 index, u32 data)
45 nb_write_index((nb_dev), NBMISC_INDEX, ((index) | 0x80), (data));
48 static u32 htiu_read_index(device_t nb_dev, u32 index)
50 return nb_read_index((nb_dev), NBHTIU_INDEX, (index));
53 static void htiu_write_index(device_t nb_dev, u32 index, u32 data)
55 nb_write_index((nb_dev), NBHTIU_INDEX, ((index) | 0x100), (data));
58 static u32 nbmc_read_index(device_t nb_dev, u32 index)
60 return nb_read_index((nb_dev), NBMC_INDEX, (index));
63 static void nbmc_write_index(device_t nb_dev, u32 index, u32 data)
65 nb_write_index((nb_dev), NBMC_INDEX, ((index) | 1 << 9), (data));
68 static void set_htiu_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask,
72 reg = reg_old = htiu_read_index(nb_dev, reg_pos);
76 htiu_write_index(nb_dev, reg_pos, reg);
80 static void set_nbmisc_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask,
84 reg = reg_old = nbmisc_read_index(nb_dev, reg_pos);
88 nbmisc_write_index(nb_dev, reg_pos, reg);
92 static void set_nbcfg_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask,
96 reg = reg_old = pci_read_config32(nb_dev, reg_pos);
100 pci_write_config32(nb_dev, reg_pos, reg);
104 static void set_nbcfg_enable_bits_8(device_t nb_dev, u32 reg_pos, u8 mask,
108 reg = reg_old = pci_read_config8(nb_dev, reg_pos);
111 if (reg != reg_old) {
112 pci_write_config8(nb_dev, reg_pos, reg);
116 static void set_nbmc_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask,
120 reg = reg_old = nbmc_read_index(nb_dev, reg_pos);
123 if (reg != reg_old) {
124 nbmc_write_index(nb_dev, reg_pos, reg);
129 * Compliant with CIM_33's ATINB_PrepareInit
131 static void get_cpu_rev(void)
133 u32 eax, ebx, ecx, edx;
134 __asm__ volatile ("cpuid":"=a" (eax), "=b"(ebx), "=c"(ecx), "=d"(edx)
136 printk(BIOS_INFO, "get_cpu_rev EAX=0x%x.\n", eax);
138 printk(BIOS_INFO, "CPU Rev is K8_Cx.\n");
139 else if (eax <= 0x10fff)
140 printk(BIOS_INFO, "CPU Rev is K8_Dx.\n");
141 else if (eax <= 0x20fff)
142 printk(BIOS_INFO, "CPU Rev is K8_Ex.\n");
143 else if (eax <= 0x40fff)
144 printk(BIOS_INFO, "CPU Rev is K8_Fx.\n");
145 else if (eax == 0x60fb1 || eax == 0x60f81) /*These two IDS are exception, they are G1. */
146 printk(BIOS_INFO, "CPU Rev is K8_G1.\n");
147 else if (eax <= 0X60FF0)
148 printk(BIOS_INFO, "CPU Rev is K8_G0.\n");
149 else if (eax <= 0x100000)
150 printk(BIOS_INFO, "CPU Rev is K8_G1.\n");
152 printk(BIOS_INFO, "CPU Rev is K8_10.\n");
155 static u8 get_nb_rev(device_t nb_dev)
158 reg = pci_read_config32(nb_dev, 0x00);
159 if (0x7911 == (reg >> 16))
161 reg = pci_read_config8(nb_dev, 0x89); /* copy from CIM, can't find in doc */
162 if (reg & 0x2) /* check bit1 */
164 if (reg & 0x1) /* check bit0 */
170 /*****************************************
171 * Compliant with CIM_33's ATINB_HTInit
172 * Init HT link speed/width for rs690 -- k8 link
173 *****************************************/
174 static void rs690_htinit(void)
177 * About HT, it has been done in enumerate_ht_chain().
179 device_t k8_f0, rs690_f0;
184 k8_f0 = PCI_DEV(0, 0x18, 0);
185 /************************
186 * get k8's ht freq, in k8's function 0, offset 0x88
187 * bit11-8, specifics the maximum operation frequency of the link's transmitter clock.
188 * The link frequency field (Frq) is cleared by cold reset. SW can write a nonzero
189 * value to this reg, and that value takes effect on the next warm reset or
190 * LDTSTOP_L disconnect sequence.
197 ************************/
198 reg = pci_read_config32(k8_f0, 0x88);
199 k8_ht_freq = (reg & 0xf00) >> 8;
200 printk(BIOS_SPEW, "rs690_htinit k8_ht_freq=%x.\n", k8_ht_freq);
201 rs690_f0 = PCI_DEV(0, 0, 0);
202 reg8 = pci_read_config8(rs690_f0, 0x9c);
203 printk(BIOS_SPEW, "rs690_htinit NB_CFG_Q_F1000_800=%x\n", reg8);
204 /* For 1000 MHz HT, NB_CFG_Q_F1000_800 bit 0 MUST be set.
205 * For any other HT frequency, NB_CFG_Q_F1000_800 bit 0 MUST NOT be set.
207 if (((k8_ht_freq == 0x6) || (k8_ht_freq == 0xf)) && (!(reg8 & 0x1))) {
208 printk(BIOS_INFO, "rs690_htinit setting bit 0 in NB_CFG_Q_F1000_800 to use 1 GHz HT\n");
210 pci_write_config8(rs690_f0, 0x9c, reg8);
211 } else if ((k8_ht_freq != 0x6) && (k8_ht_freq != 0xf) && (reg8 & 0x1)) {
212 printk(BIOS_INFO, "rs690_htinit clearing bit 0 in NB_CFG_Q_F1000_800 to not use 1 GHz HT\n");
214 pci_write_config8(rs690_f0, 0x9c, reg8);
218 /*******************************************************
219 * Optimize k8 with UMA.
220 * See BKDG_NPT_0F guide for details.
221 * The processor node is addressed by its Node ID on the HT link and can be
222 * accessed with a device number in the PCI configuration space on Bus0.
223 * The Node ID 0 is mapped to Device 24 (0x18), the Node ID 1 is mapped
224 * to Device 25, and so on.
225 * The processor implements configuration registers in PCI configuration
226 * space using the following four headers
227 * Function0: HT technology configuration
228 * Function1: Address map configuration
229 * Function2: DRAM and HT technology Trace mode configuration
230 * Function3: Miscellaneous configuration
231 *******************************************************/
232 static void k8_optimization(void)
234 device_t k8_f0, k8_f2, k8_f3;
237 printk(BIOS_INFO, "k8_optimization()\n");
238 k8_f0 = PCI_DEV(0, 0x18, 0);
239 k8_f2 = PCI_DEV(0, 0x18, 2);
240 k8_f3 = PCI_DEV(0, 0x18, 3);
242 pci_write_config32(k8_f0, 0x90, 0x01700178); /* CIM NPT_Optimization */
243 set_nbcfg_enable_bits(k8_f0, 0x68, 1 << 28, 0 << 28);
244 set_nbcfg_enable_bits(k8_f0, 0x68, 1 << 26 | 1 << 27,
246 set_nbcfg_enable_bits(k8_f0, 0x68, 1 << 11, 1 << 11);
247 set_nbcfg_enable_bits(k8_f0, 0x84, 1 << 11 | 1 << 13 | 1 << 15, 1 << 11 | 1 << 13 | 1 << 15); /* TODO */
249 pci_write_config32(k8_f3, 0x70, 0x51320111); /* CIM NPT_Optimization */
250 pci_write_config32(k8_f3, 0x74, 0x50304021);
251 pci_write_config32(k8_f3, 0x78, 0x08002A00);
252 if (pci_read_config32(k8_f3, 0xE8) & 0x3<<12)
253 pci_write_config32(k8_f3, 0x7C, 0x0000211B); /* dual core */
255 pci_write_config32(k8_f3, 0x7C, 0x0000211C); /* single core */
256 set_nbcfg_enable_bits_8(k8_f3, 0xDC, 0xFF, 0x25);
258 set_nbcfg_enable_bits(k8_f2, 0xA0, 1 << 5, 1 << 5);
259 set_nbcfg_enable_bits(k8_f2, 0x94, 0xF << 24, 7 << 24);
260 set_nbcfg_enable_bits(k8_f2, 0x90, 1 << 10, 1 << 10);
261 set_nbcfg_enable_bits(k8_f2, 0xA0, 3 << 2, 3 << 2);
262 set_nbcfg_enable_bits(k8_f2, 0xA0, 1 << 5, 1 << 5);
264 msr = rdmsr(0xC001001F);
267 wrmsr(0xC001001F, msr);
270 /*****************************************
271 * Compliant with CIM_33's ATINB_PCICFG_POR_TABLE
272 *****************************************/
273 static void rs690_por_pcicfg_init(device_t nb_dev)
275 /* enable PCI Memory Access */
276 set_nbcfg_enable_bits_8(nb_dev, 0x04, (u8)(~0xFD), 0x02);
277 /* Set RCRB Enable */
278 set_nbcfg_enable_bits_8(nb_dev, 0x84, (u8)(~0xFF), 0x1);
279 /* allow decode of 640k-1MB */
280 set_nbcfg_enable_bits_8(nb_dev, 0x84, (u8)(~0xEF), 0x10);
281 /* Enable PM2_CNTL(BAR2) IO mapped cfg write access to be broadcast to both NB and SB */
282 set_nbcfg_enable_bits_8(nb_dev, 0x84, (u8)(~0xFF), 0x4);
283 /* Power Management Register Enable */
284 set_nbcfg_enable_bits_8(nb_dev, 0x84, (u8)(~0xFF), 0x80);
286 /* Reg4Ch[1]=1 (APIC_ENABLE) force cpu request with address 0xFECx_xxxx to south-bridge
287 * Reg4Ch[6]=1 (BMMsgEn) enable BM_Set message generation
289 set_nbcfg_enable_bits_8(nb_dev, 0x4C, (u8)(~0x00), 0x42 | 1);
291 /* Reg4Ch[16]=1 (WakeC2En) enable Wake_from_C2 message generation.
292 * Reg4Ch[18]=1 (P4IntEnable) Enable north-bridge to accept MSI with address 0xFEEx_xxxx from south-bridge */
293 set_nbcfg_enable_bits_8(nb_dev, 0x4E, (u8)(~0xFF), 0x05);
294 /* Reg94h[4:0] = 0x0 P drive strength offset 0
295 * Reg94h[6:5] = 0x2 P drive strength additive adjust */
296 set_nbcfg_enable_bits_8(nb_dev, 0x94, (u8)(~0x80), 0x40);
298 /* Reg94h[20:16] = 0x0 N drive strength offset 0
299 * Reg94h[22:21] = 0x2 N drive strength additive adjust */
300 set_nbcfg_enable_bits_8(nb_dev, 0x96, (u8)(~0x80), 0x40);
302 /* Reg80h[4:0] = 0x0 Termination offset
303 * Reg80h[6:5] = 0x2 Termination additive adjust */
304 set_nbcfg_enable_bits_8(nb_dev, 0x80, (u8)(~0x80), 0x40);
306 /* Reg80h[14] = 0x1 Enable receiver termination control */
307 set_nbcfg_enable_bits_8(nb_dev, 0x81, (u8)(~0xFF), 0x40);
309 /* Reg94h[15] = 0x1 Enables HT transmitter advanced features to be turned on
310 * Reg94h[14] = 0x1 Enable drive strength control */
311 set_nbcfg_enable_bits_8(nb_dev, 0x95, (u8)(~0x3F), 0xC4);
313 /* Reg94h[31:29] = 0x7 Enables HT transmitter de-emphasis */
314 set_nbcfg_enable_bits_8(nb_dev, 0x97, (u8)(~0x1F), 0xE0);
316 /*Reg8Ch[10:9] = 0x3 Enables Gfx Debug BAR,
317 * force this BAR as mem type in rs690_gfx.c */
318 set_nbcfg_enable_bits_8(nb_dev, 0x8D, (u8)(~0xFF), 0x03);
322 /*****************************************
323 * Compliant with CIM_33's ATINB_MCIndex_POR_TABLE
324 *****************************************/
325 static void rs690_por_mc_index_init(device_t nb_dev)
327 set_nbmc_enable_bits(nb_dev, 0x7A, ~0xFFFFFF80, 0x0000005F);
328 set_nbmc_enable_bits(nb_dev, 0xD8, ~0x00000000, 0x00600060);
329 set_nbmc_enable_bits(nb_dev, 0xD9, ~0x00000000, 0x00600060);
330 set_nbmc_enable_bits(nb_dev, 0xE0, ~0x00000000, 0x00000000);
331 set_nbmc_enable_bits(nb_dev, 0xE1, ~0x00000000, 0x00000000);
332 set_nbmc_enable_bits(nb_dev, 0xE8, ~0x00000000, 0x003E003E);
333 set_nbmc_enable_bits(nb_dev, 0xE9, ~0x00000000, 0x003E003E);
336 /*****************************************
337 * Compliant with CIM_33's ATINB_MISCIND_POR_TABLE
338 * Compliant with CIM_33's MISC_INIT_TBL
339 *****************************************/
340 static void rs690_por_misc_index_init(device_t nb_dev)
342 /* NB_MISC_IND_WR_EN + IOC_PCIE_CNTL
343 * Block non-snoop DMA request if PMArbDis is set.
345 set_nbmisc_enable_bits(nb_dev, 0x0B, ~0xFFFF0000, 0x00000180);
346 set_nbmisc_enable_bits(nb_dev, 0x01, ~0xFFFFFFFF, 0x00000040);
348 /* NBCFG (NBMISCIND 0x0): NB_CNTL -
349 * HIDE_NB_AGP_CAP ([0], default=1)HIDE
350 * HIDE_P2P_AGP_CAP ([1], default=1)HIDE
351 * HIDE_NB_GART_BAR ([2], default=1)HIDE
352 * AGPMODE30 ([4], default=0)DISABLE
353 * AGP30ENCHANCED ([5], default=0)DISABLE
354 * HIDE_AGP_CAP ([8], default=1)ENABLE */
355 set_nbmisc_enable_bits(nb_dev, 0x00, ~0xFFFF0000, 0x00000506); /* set bit 10 for MSI */
357 /* NBMISCIND:0x6A[16]= 1 SB link can get a full swing
358 * set_nbmisc_enable_bits(nb_dev, 0x6A, 0ffffffffh, 000010000);
359 * NBMISCIND:0x6A[17]=1 Set CMGOOD_OVERRIDE. */
360 set_nbmisc_enable_bits(nb_dev, 0x6A, ~0xffffffff, 0x00020000);
362 /* NBMISIND:0x40 Bit[8]=1 and Bit[10]=1 following bits are required to set in order to allow LVDS or PWM features to work. */
363 set_nbmisc_enable_bits(nb_dev, 0x40, ~0xffffffff, 0x00000500);
365 /* NBMISIND:0xC Bit[13]=1 Enable GSM mode for C1e or C3 with pop-up. */
366 set_nbmisc_enable_bits(nb_dev, 0x0C, ~0xffffffff, 0x00002000);
368 /* Set NBMISIND:0x1F[3] to map NB F2 interrupt pin to INTB# */
369 set_nbmisc_enable_bits(nb_dev, 0x1F, ~0xffffffff, 0x00000008);
371 /* Compliant with CIM_33's MISC_INIT_TBL, except Hide NB_BAR3_PCIE
372 * Enable access to DEV8
373 * Enable setPower message for all ports
375 set_nbmisc_enable_bits(nb_dev, 0x00, 1 << 6, 1 << 6);
376 set_nbmisc_enable_bits(nb_dev, 0x0b, 1 << 20, 1 << 20);
377 set_nbmisc_enable_bits(nb_dev, 0x51, 1 << 20, 1 << 20);
378 set_nbmisc_enable_bits(nb_dev, 0x53, 1 << 20, 1 << 20);
379 set_nbmisc_enable_bits(nb_dev, 0x55, 1 << 20, 1 << 20);
380 set_nbmisc_enable_bits(nb_dev, 0x57, 1 << 20, 1 << 20);
381 set_nbmisc_enable_bits(nb_dev, 0x59, 1 << 20, 1 << 20);
382 set_nbmisc_enable_bits(nb_dev, 0x5B, 1 << 20, 1 << 20);
384 set_nbmisc_enable_bits(nb_dev, 0x00, 1 << 7, 1 << 7);
385 set_nbmisc_enable_bits(nb_dev, 0x07, 0x000000f0, 0x30);
386 /* Disable bus-master trigger event from SB and Enable set_slot_power message to SB */
387 set_nbmisc_enable_bits(nb_dev, 0x0B, 0xffffffff, 0x500180);
390 /*****************************************
391 * Compliant with CIM_33's ATINB_HTIUNBIND_POR_TABLE
392 *****************************************/
393 static void rs690_por_htiu_index_init(device_t nb_dev)
396 * Enables GSM mode for C1e or C3 with pop-up
397 * Prevents AllowLdtStop from being asserted during HT link recovery
398 * Allows FID cycles to be serviced faster. Needed for RS690 A12. No harm in RS690 A11 */
399 set_htiu_enable_bits(nb_dev, 0x05, ~0xffffffff, 0x0BC);
401 * Enables writes to pass in-progress reads
402 * Enables streaming of CPU writes
403 * Enables extended write buffer for CPU writes
404 * Enables additional response buffers
405 * Enables special reads to pass writes
406 * Enables decoding of C1e/C3 and FID cycles
407 * Enables HTIU-display handshake bypass.
408 * Enables tagging fix */
409 set_htiu_enable_bits(nb_dev, 0x06, ~0xFFFFFFFE, 0x4203A202);
411 /* Enables byte-write optimization for IOC requests
412 * Disables delaying STPCLK de-assert during FID sequence. Needed when enhanced UMA arbitration is used.
413 * Disables upstream system-management delay */
414 set_htiu_enable_bits(nb_dev, 0x07, ~0xFFFFFFF9, 0x001);
416 /* HTIUNBIND 0x16 [1] = 0x1 Enable crc decoding fix */
417 set_htiu_enable_bits(nb_dev, 0x16, ~0xFFFFFFFF, 0x2);
420 /*****************************************
421 * Compliant with CIM_33's ATINB_POR_INIT_JMPDI
422 * Configure RS690 registers to power-on default RPR.
423 * POR: Power On Reset
424 * RPR: Register Programming Requirements
425 *****************************************/
426 static void rs690_por_init(device_t nb_dev)
428 printk(BIOS_INFO, "rs690_por_init\n");
429 /* ATINB_PCICFG_POR_TABLE, initialize the values for rs690 PCI Config registers */
430 rs690_por_pcicfg_init(nb_dev);
432 /* ATINB_MCIND_POR_TABLE */
433 rs690_por_mc_index_init(nb_dev);
435 /* ATINB_MISCIND_POR_TABLE */
436 rs690_por_misc_index_init(nb_dev);
438 /* ATINB_HTIUNBIND_POR_TABLE */
439 rs690_por_htiu_index_init(nb_dev);
441 /* ATINB_CLKCFG_PORT_TABLE */
442 /* rs690 A11 SB Link full swing? */
445 /* enable CFG access to Dev8, which is the SB P2P Bridge */
446 static void enable_rs690_dev8(void)
448 set_nbmisc_enable_bits(PCI_DEV(0, 0, 0), 0x00, 1 << 6, 1 << 6);
454 * Compliant with CIM_33's AtiNBInitEarlyPost (AtiInitNBBeforePCIInit).
456 static void rs690_before_pci_init(void)
461 * The calling sequence is same as CIM.
463 static void rs690_early_setup(void)
465 device_t nb_dev = PCI_DEV(0, 0, 0);
466 printk(BIOS_INFO, "rs690_early_setup()\n");
468 /*ATINB_PrepareInit */
470 switch (get_nb_rev(nb_dev)) { /* PCIEMiscInit */
472 printk(BIOS_INFO, "NB Revision is A11.\n");
475 printk(BIOS_INFO, "NB Revision is A12.\n");
478 printk(BIOS_INFO, "NB Revision is A21.\n");
483 rs690_por_init(nb_dev);