2 * This file is part of the coreboot project.
4 * Copyright (C) 2007 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 * cs5536_early_setup.c: Early chipset initialization for CS5536 companion device
22 * This file implements the initialization sequence documented in section 4.2 of
23 * AMD Geode GX Processor CS5536 Companion Device GoedeROM Porting Guide.
27 * @brief Setup PCI IDSEL for CS5536
29 static void cs5536_setup_extmsr(void)
33 /* forward MSR access to CS5536_GLINK_PORT_NUM to CS5536_DEV_NUM */
34 msr.hi = msr.lo = 0x00000000;
35 if (CS5536_GLINK_PORT_NUM <= 4) {
36 msr.lo = CS5536_DEV_NUM <<
37 (unsigned char)((CS5536_GLINK_PORT_NUM - 1) * 8);
39 msr.hi = CS5536_DEV_NUM <<
40 (unsigned char)((CS5536_GLINK_PORT_NUM - 5) * 8);
42 wrmsr(GLPCI_ExtMSR, msr);
45 static void cs5536_setup_idsel(void)
47 /* write IDSEL to the write once register at address 0x0000 */
48 outl(0x1 << (CS5536_DEV_NUM + 10), 0);
51 static void cs5536_usb_swapsif(void)
55 msr = rdmsr(USB1_SB_GLD_MSR_CAP + 0x5);
56 //USB Serial short detect bit.
58 /* We need to preserve bits 32,33,35 and not clear any BIST
59 * error, but clear the SERSHRT error bit */
62 wrmsr(USB1_SB_GLD_MSR_CAP + 0x5, msr);
66 static void cs5536_setup_iobase(void)
69 /* setup LBAR for SMBus controller */
71 msr.lo = SMBUS_IO_BASE;
72 wrmsr(MDD_LBAR_SMB, msr);
74 /* setup LBAR for GPIO */
76 msr.lo = GPIO_IO_BASE;
77 wrmsr(MDD_LBAR_GPIO, msr);
79 /* setup LBAR for MFGPT */
81 msr.lo = MFGPT_IO_BASE;
82 wrmsr(MDD_LBAR_MFGPT, msr);
84 /* setup LBAR for ACPI */
86 msr.lo = ACPI_IO_BASE;
87 wrmsr(MDD_LBAR_ACPI, msr);
89 /* setup LBAR for PM Support */
92 wrmsr(MDD_LBAR_PMS, msr);
95 static void cs5536_setup_power_button(void)
97 /* Power Button Setup */
98 outl(0x40020000, PMS_IO_BASE + 0x40);
100 /* setup WORK_AUX/GPIO24, it is the external signal for 5536
101 * vsb_work_aux controls all voltage rails except Vstandby & Vmem.
102 * We need to enable, OUT_AUX1 and OUTPUT_ENABLE in this order.
103 * If WORK_AUX/GPIO24 is not enabled then soft-off will not work.
105 outl(GPIOH_24_SET, GPIO_IO_BASE + GPIOH_OUT_AUX1_SELECT);
106 outl(GPIOH_24_SET, GPIO_IO_BASE + GPIOH_OUTPUT_ENABLE);
110 static void cs5536_setup_gpio(void)
114 /* setup GPIO pins 14/15 for SDA/SCL */
115 val = GPIOL_15_SET | GPIOL_14_SET;
117 outl(val, GPIO_IO_BASE + GPIOL_OUT_AUX1_SELECT);
119 outl(val, GPIO_IO_BASE + GPIOL_OUTPUT_ENABLE);
121 outl(val, GPIO_IO_BASE + GPIOL_IN_AUX1_SELECT);
123 outl(val, GPIO_IO_BASE + GPIOL_INPUT_ENABLE);
126 static void cs5536_disable_internal_uart(void)
129 /* The UARTs default to enabled.
130 * Disable and reset them and configure them later. (SIO init)
132 msr = rdmsr(MDD_UART1_CONF);
134 wrmsr(MDD_UART1_CONF, msr);
135 msr.lo = 0; // disabled
136 wrmsr(MDD_UART1_CONF, msr);
138 msr = rdmsr(MDD_UART2_CONF);
140 wrmsr(MDD_UART2_CONF, msr);
141 msr.lo = 0; // disabled
142 wrmsr(MDD_UART2_CONF, msr);
145 static void cs5536_setup_cis_mode(void)
149 /* setup CPU interface serial to mode B to match CPU */
150 msr = rdmsr(GLPCI_SB_CTRL);
153 wrmsr(GLPCI_SB_CTRL, msr);
156 /* see page 412 of the cs5536 companion book */
157 static void cs5536_setup_onchipuart(void)
161 /* Setup early for polling only mode.
162 * 1. Eanble GPIO 8 to OUT_AUX1, 9 to IN_AUX1
163 * GPIO LBAR + 0x04, LBAR + 0x10, LBAR + 0x20, LBAR + 34
164 * 2. Enable UART IO space in MDD
165 * MSR 0x51400014 bit 18:16
166 * 3. Enable UART controller
167 * MSR 0x5140003A bit 0, 1
170 /* GPIO8 - UART1_TX */
171 /* Set: Output Enable (0x4) */
172 outl(GPIOL_8_SET, GPIO_IO_BASE + GPIOL_OUTPUT_ENABLE);
173 /* Set: OUTAUX1 Select (0x10) */
174 outl(GPIOL_8_SET, GPIO_IO_BASE + GPIOL_OUT_AUX1_SELECT);
175 /* GPIO9 - UART1_RX */
176 /* Set: Input Enable (0x20) */
177 outl(GPIOL_9_SET, GPIO_IO_BASE + GPIOL_INPUT_ENABLE);
178 /* Set: INAUX1 Select (0x34) */
179 outl(GPIOL_9_SET, GPIO_IO_BASE + GPIOL_IN_AUX1_SELECT);
181 /* set address to 3F8 */
182 msr = rdmsr(MDD_LEG_IO);
184 wrmsr(MDD_LEG_IO, msr);
186 /* Bit 1 = DEVEN (device enable)
187 * Bit 4 = EN_BANKS (allow access to the upper banks
189 msr.lo = (1 << 4) | (1 << 1);
193 wrmsr(MDD_UART1_CONF, msr);
196 /* note: you can't do prints in here in most cases,
197 * and we don't want to hang on serial, so they are
200 static void cs5536_early_setup(void)
204 cs5536_setup_extmsr();
205 cs5536_setup_cis_mode();
207 msr = rdmsr(GLCP_SYS_RSTPLL);
208 if (msr.lo & (0x3f << 26)) {
209 /* PLL is already set and we are reboot from PLL reset */
210 //print_debug("reboot from BIOS reset\n\r");
213 //print_debug("Setup idsel\r\n");
214 cs5536_setup_idsel();
215 //print_debug("Setup iobase\r\n");
216 cs5536_usb_swapsif();
217 cs5536_setup_iobase();
218 //print_debug("Setup gpio\r\n");
220 //print_debug("Setup smbus\r\n");
221 cs5536_enable_smbus();
222 //print_debug("Setup power button\r\n");
223 cs5536_setup_power_button();