1 #include <cpu/amd/gx2def.h>
5 * cs5536_early_setup.c: Early chipset initialization for CS5536 companion device
8 * This file implements the initialization sequence documented in section 4.2 of
9 * AMD Geode GX Processor CS5536 Companion Device GoedeROM Porting Guide.
13 #define CS5536_GLINK_PORT_NUM 0x02 /* the geode link port number to the CS5536 */
14 #define CS5536_DEV_NUM 0x0F /* default PCI device number for CS5536 */
17 * @brief Setup PCI IDSEL for CS5536
22 static void cs5536_setup_extmsr(void)
26 /* forward MSR access to CS5536_GLINK_PORT_NUM to CS5536_DEV_NUM */
27 msr.hi = msr.lo = 0x00000000;
28 if (CS5536_GLINK_PORT_NUM <= 4) {
29 msr.lo = CS5536_DEV_NUM << ((CS5536_GLINK_PORT_NUM - 1) * 8);
31 msr.hi = CS5536_DEV_NUM << ((CS5536_GLINK_PORT_NUM - 5) * 8);
33 wrmsr(0x5000201e, msr);
36 static void cs5536_setup_idsel(void)
38 /* write IDSEL to the write once register at address 0x0000 */
39 outl(0x1 << (CS5536_DEV_NUM + 10), 0);
42 static void cs5536_usb_swapsif(void)
46 msr = rdmsr(0x51600005);
47 //USB Serial short detect bit.
49 /* We need to preserve bits 32,33,35 and not clear any BIST error, but clear the
50 * SERSHRT error bit */
52 wrmsr(0x51600005, msr);
56 static int cs5536_setup_iobase(void)
60 /* setup LBAR for SMBus controller */
61 __builtin_wrmsr(0x5140000b, 0x00006000, 0x0000f001);
62 /* setup LBAR for GPIO */
63 __builtin_wrmsr(0x5140000c, 0x00006100, 0x0000f001);
64 /* setup LBAR for MFGPT */
65 __builtin_wrmsr(0x5140000d, 0x00006200, 0x0000f001);
66 /* setup LBAR for ACPI */
67 __builtin_wrmsr(0x5140000e, 0x00009c00, 0x0000f001);
68 /* setup LBAR for PM Support */
69 __builtin_wrmsr(0x5140000f, 0x00009d00, 0x0000f001);
72 static void cs5536_setup_power_bottun(void)
74 /* not implemented yet */
80 ;mov eax, 0C0020000h ; 4 seconds + lock
81 mov eax, 040020000h ; 4 seconds no lock
82 mov dx, PMLogic_BASE + 40h
85 ; setup GPIO24, it is the external signal for 5536 vsb_work_aux
86 ; which controls all voltage rails except Vstandby & Vmem.
87 ; We need to enable, OUT_AUX1 and OUTPUT_ENABLE in this order.
88 ; If GPIO24 is not enabled then soft-off will not work.
89 mov dx, GPIOH_OUT_AUX1_SELECT
92 mov dx, GPIOH_OUTPUT_ENABLE
98 static void cs5536_setup_gpio(void)
102 /* setup GPIO pins 14/15 for SDA/SCL */
103 val = (1<<14 | 1<<15);
105 outl(0x3fffc000, 0x6100 + 0x04);
106 //outl(val, 0x6100 + 0x04);
108 outl(0x3fffc000, 0x6100 + 0x10);
109 //outl(val, 0x6100 + 0x10);
111 //outl(0x0f5af0a5, 0x6100 + 0x20);
112 outl(0x3fffc000, 0x6100 + 0x20);
113 //outl(val, 0x6100 + 0x20);
115 //outl(0x3ffbc004, 0x6100 + 0x34);
116 outl(0x3fffc000, 0x6100 + 0x34);
117 //outl(val, 0x6100 + 0x34);
120 /* changes proposed by Ollie; we will test this later. */
121 /* setup GPIO pins 14/15 for SDA/SCL */
122 val = GPIOL_15_SET | GPIOL_14_SET;
124 //outl(0x3fffc000, 0x6100 + 0x04);
125 outl(val, 0x6100 + 0x04);
127 //outl(0x3fffc000, 0x6100 + 0x10);
128 outl(val, 0x6100 + 0x10);
130 //outl(0x3fffc000, 0x6100 + 0x20);
131 outl(val, 0x6100 + 0x20);
133 //outl(0x3fffc000, 0x6100 + 0x34);
134 outl(val, 0x6100 + 0x34);
138 static void cs5536_disable_internal_uart(void)
140 /* not implemented yet */
142 ; The UARTs default to enabled.
143 ; Disable and reset them and configure them later. (SIO init)
144 mov ecx, MDD_UART1_CONF
148 mov eax, 0h ; disabled
151 mov ecx, MDD_UART2_CONF
155 mov eax, 0h ; disabled
161 static void cs5536_setup_cis_mode(void)
165 /* setup CPU interface serial to mode C on both sides */
166 msr = __builtin_rdmsr(0x51000010);
169 __builtin_wrmsr(0x51000010, msr.lo, msr.hi);
170 //Only do this if we are building for 5536
171 __builtin_wrmsr(0x54002010, 0x00000002, 0x00000000);
174 static void dummy(void)
178 /* see page 412 of the cs5536 companion book */
179 static int cs5536_setup_onchipuart(void)
183 * 1. Eanble GPIO 8 to OUT_AUX1, 9 to IN_AUX1
184 * GPIO LBAR + 0x04, LBAR + 0x10, LBAR + 0x20, LBAR + 34
185 * 2. Enable UART IO space in MDD
186 * MSR 0x51400014 bit 18:16
187 * 3. Enable UART controller
188 * MSR 0x5140003A bit 0, 1
189 * 4. IRQ routing on IRQ Mapper
190 * MSR 0x51400021 bit [27:24]
195 /* This enables COM2, but that should be done elsewhere
196 wrmsr(0x5140003e, msr);
201 wrmsr(0x5140003a, msr);
202 /* GPIO8 - UART1_TX */
203 /* Set: Output Enable (0x4) */
204 m = inl(GPIOL_OUTPUT_ENABLE);
207 outl(m,GPIOL_OUTPUT_ENABLE);
208 /* Set: OUTAUX1 Select (0x10) */
209 m = inl(GPIOL_OUT_AUX1_SELECT);
212 outl(m,GPIOL_OUT_AUX1_SELECT);
213 /* Set: Pull Up (0x18) */
214 m = inl(GPIOL_PULLUP_ENABLE);
217 /* GPIO9 - UART1_RX */
218 /* Set: Pull Up (0x18) */
221 outl(m,GPIOL_PULLUP_ENABLE);
222 /* Set: Input Enable (0x20) */
223 m = inl(GPIOL_INPUT_ENABLE);
226 outl(m,GPIOL_INPUT_ENABLE);
227 /* Set: INAUX1 Select (0x34) */
228 m = inl(GPIOL_IN_AUX1_SELECT);
231 outl(m,GPIOL_IN_AUX1_SELECT);
233 msr = rdmsr(MDD_LEG_IO);
235 wrmsr(MDD_LEG_IO,msr);
238 /* note: you can't do prints in here in most cases,
239 * and we don't want to hang on serial, so they are
242 static int cs5536_early_setup(void)
246 cs5536_setup_extmsr();
248 msr = rdmsr(GLCP_SYS_RSTPLL);
249 if (msr.lo & (0x3f << 26)) {
250 /* PLL is already set and we are reboot from PLL reset */
251 //print_debug("reboot from BIOS reset\n\r");
254 //print_debug("Setup idsel\r\n");
255 cs5536_setup_idsel();
256 //print_debug("Setup iobase\r\n");
257 cs5536_usb_swapsif();
258 cs5536_setup_iobase();
259 //print_debug("Setup gpio\r\n");
261 //print_debug("Setup cis_mode\r\n");
262 cs5536_setup_cis_mode();
263 //print_debug("Setup smbus\r\n");
264 cs5536_enable_smbus();