4 * cs5536_early_setup.c: Early chipset initialization for CS5536 companion device
7 * This file implements the initialization sequence documented in section 4.2 of
8 * AMD Geode GX Processor CS5536 Companion Device GoedeROM Porting Guide.
12 #define CS5536_GLINK_PORT_NUM 0x02 /* the geode link port number to the CS5536 */
13 #define CS5536_DEV_NUM 0x0F /* default PCI device number for CS5536 */
16 * @brief Setup PCI IDSEL for CS5536
21 static void cs5536_setup_extmsr(void)
25 /* forward MSR access to CS5536_GLINK_PORT_NUM to CS5536_DEV_NUM */
26 msr.hi = msr.lo = 0x00000000;
27 if (CS5536_GLINK_PORT_NUM <= 4) {
28 msr.lo = CS5536_DEV_NUM << ((CS5536_GLINK_PORT_NUM - 1) * 8);
30 msr.hi = CS5536_DEV_NUM << ((CS5536_GLINK_PORT_NUM - 5) * 8);
32 wrmsr(0x5000201e, msr);
35 static void cs5536_setup_idsel(void)
37 /* write IDSEL to the write once register at address 0x0000 */
38 outl(0x1 << (CS5536_DEV_NUM + 10), 0);
41 static void cs5536_usb_swapsif(void)
45 msr = rdmsr(0x51600005);
46 //USB Serial short detect bit.
48 /* We need to preserve bits 32,33,35 and not clear any BIST error, but clear the
49 * SERSHRT error bit */
51 wrmsr(0x51600005, msr);
55 static int cs5536_setup_iobase(void)
59 /* setup LBAR for SMBus controller */
60 __builtin_wrmsr(0x5140000b, 0x00006000, 0x0000f001);
61 /* setup LBAR for GPIO */
62 __builtin_wrmsr(0x5140000c, 0x00006100, 0x0000f001);
63 /* setup LBAR for MFGPT */
64 __builtin_wrmsr(0x5140000d, 0x00006200, 0x0000f001);
65 /* setup LBAR for ACPI */
66 __builtin_wrmsr(0x5140000e, 0x00009c00, 0x0000f001);
67 /* setup LBAR for PM Support */
68 __builtin_wrmsr(0x5140000f, 0x00009d00, 0x0000f001);
71 static void cs5536_setup_power_bottun(void)
73 /* not implemented yet */
79 ;mov eax, 0C0020000h ; 4 seconds + lock
80 mov eax, 040020000h ; 4 seconds no lock
81 mov dx, PMLogic_BASE + 40h
84 ; setup GPIO24, it is the external signal for 5536 vsb_work_aux
85 ; which controls all voltage rails except Vstandby & Vmem.
86 ; We need to enable, OUT_AUX1 and OUTPUT_ENABLE in this order.
87 ; If GPIO24 is not enabled then soft-off will not work.
88 mov dx, GPIOH_OUT_AUX1_SELECT
91 mov dx, GPIOH_OUTPUT_ENABLE
97 static void cs5536_setup_gpio(void)
101 /* setup GPIO pins 14/15 for SDA/SCL */
102 val = (1<<14 | 1<<15);
104 outl(0x3fffc000, 0x6100 + 0x04);
105 //outl(val, 0x6100 + 0x04);
107 outl(0x3fffc000, 0x6100 + 0x10);
108 //outl(val, 0x6100 + 0x10);
110 //outl(0x0f5af0a5, 0x6100 + 0x20);
111 outl(0x3fffc000, 0x6100 + 0x20);
112 //outl(val, 0x6100 + 0x20);
114 //outl(0x3ffbc004, 0x6100 + 0x34);
115 outl(0x3fffc000, 0x6100 + 0x34);
116 //outl(val, 0x6100 + 0x34);
119 /* changes proposed by Ollie; we will test this later. */
120 /* setup GPIO pins 14/15 for SDA/SCL */
121 val = GPIOL_15_SET | GPIOL_14_SET;
123 //outl(0x3fffc000, 0x6100 + 0x04);
124 outl(val, 0x6100 + 0x04);
126 //outl(0x3fffc000, 0x6100 + 0x10);
127 outl(val, 0x6100 + 0x10);
129 //outl(0x3fffc000, 0x6100 + 0x20);
130 outl(val, 0x6100 + 0x20);
132 //outl(0x3fffc000, 0x6100 + 0x34);
133 outl(val, 0x6100 + 0x34);
137 static void cs5536_disable_internal_uart(void)
139 /* not implemented yet */
141 ; The UARTs default to enabled.
142 ; Disable and reset them and configure them later. (SIO init)
143 mov ecx, MDD_UART1_CONF
147 mov eax, 0h ; disabled
150 mov ecx, MDD_UART2_CONF
154 mov eax, 0h ; disabled
160 static void cs5536_setup_cis_mode(void)
164 /* setup CPU interface serial to mode C on both sides */
165 msr = __builtin_rdmsr(0x51000010);
168 __builtin_wrmsr(0x51000010, msr.lo, msr.hi);
169 //Only do this if we are building for 5536
170 __builtin_wrmsr(0x54002010, 0x00000002, 0x00000000);
173 static void dummy(void)
177 /* see page 412 of the cs5536 companion book */
178 static int cs5536_setup_onchipuart(void)
182 * 1. Eanble GPIO 8 to OUT_AUX1, 9 to IN_AUX1
183 * GPIO LBAR + 0x04, LBAR + 0x10, LBAR + 0x20, LBAR + 34
184 * 2. Enable UART IO space in MDD
185 * MSR 0x51400014 bit 18:16
186 * 3. Enable UART controller
187 * MSR 0x5140003A bit 0, 1
188 * 4. IRQ routing on IRQ Mapper
189 * MSR 0x51400021 bit [27:24]
193 /* Bit 1 = DEVEN (device enable)
194 * Bit 4 = EN_BANKS (allow access to the upper banks)
197 msr.lo = (1 << 4) | (1 << 1);
199 /* This enables COM2, but that should be done elsewhere
200 wrmsr(0x5140003e, msr);
205 wrmsr(0x5140003a, msr);
206 /* GPIO8 - UART1_TX */
207 /* Set: Output Enable (0x4) */
208 m = inl(GPIOL_OUTPUT_ENABLE);
211 outl(m,GPIOL_OUTPUT_ENABLE);
212 /* Set: OUTAUX1 Select (0x10) */
213 m = inl(GPIOL_OUT_AUX1_SELECT);
216 outl(m,GPIOL_OUT_AUX1_SELECT);
217 /* Set: Pull Up (0x18) */
218 m = inl(GPIOL_PULLUP_ENABLE);
221 /* GPIO9 - UART1_RX */
222 /* Set: Pull Up (0x18) */
225 outl(m,GPIOL_PULLUP_ENABLE);
226 /* Set: Input Enable (0x20) */
227 m = inl(GPIOL_INPUT_ENABLE);
230 outl(m,GPIOL_INPUT_ENABLE);
231 /* Set: INAUX1 Select (0x34) */
232 m = inl(GPIOL_IN_AUX1_SELECT);
235 outl(m,GPIOL_IN_AUX1_SELECT);
237 msr = rdmsr(MDD_LEG_IO);
239 wrmsr(MDD_LEG_IO,msr);
242 /* note: you can't do prints in here in most cases,
243 * and we don't want to hang on serial, so they are
246 static int cs5536_early_setup(void)
250 cs5536_setup_extmsr();
252 msr = rdmsr(GLCP_SYS_RSTPLL);
253 if (msr.lo & (0x3f << 26)) {
254 /* PLL is already set and we are reboot from PLL reset */
255 //print_debug("reboot from BIOS reset\n\r");
258 //print_debug("Setup idsel\r\n");
259 cs5536_setup_idsel();
260 //print_debug("Setup iobase\r\n");
261 cs5536_usb_swapsif();
262 cs5536_setup_iobase();
263 //print_debug("Setup gpio\r\n");
265 //print_debug("Setup cis_mode\r\n");
266 cs5536_setup_cis_mode();
267 //print_debug("Setup smbus\r\n");
268 cs5536_enable_smbus();