2 * This file is part of the coreboot project.
4 * Copyright (C) 2007 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 #include <device/device.h>
22 #include <device/pci.h>
23 #include <device/pci_ops.h>
24 #include <device/pci_ids.h>
25 #include <console/console.h>
27 #include <pc80/isa-dma.h>
28 #include <pc80/mc146818rtc.h>
29 #include <pc80/i8259.h>
30 #include <cpu/x86/msr.h>
31 #include <cpu/amd/vr.h>
32 #include <cpu/amd/geode_post_code.h>
42 /* Master Configuration Register for Bus Masters.*/
43 struct msrinit SB_MASTER_CONF_TABLE[] = {
44 {USB2_SB_GLD_MSR_CONF, {.hi = 0,.lo = 0x00008f000}},
45 {ATA_SB_GLD_MSR_CONF, {.hi = 0,.lo = 0x00048f000}},
46 {AC97_SB_GLD_MSR_CONF, {.hi = 0,.lo = 0x00008f000}},
47 {MDD_SB_GLD_MSR_CONF, {.hi = 0,.lo = 0x00000f000}},
51 /* 5536 Clock Gating*/
52 struct msrinit CS5536_CLOCK_GATING_TABLE[] = {
54 {GLIU_SB_GLD_MSR_PM, {.hi = 0,.lo = 0x000000004}},
55 {GLPCI_SB_GLD_MSR_PM, {.hi = 0,.lo = 0x000000005}},
56 {GLCP_SB_GLD_MSR_PM, {.hi = 0,.lo = 0x000000004}},
57 {MDD_SB_GLD_MSR_PM, {.hi = 0,.lo = 0x050554111}}, /* SMBus clock gating errata (PBZ 2226 & SiBZ 3977) */
58 {ATA_SB_GLD_MSR_PM, {.hi = 0,.lo = 0x000000005}},
59 {AC97_SB_GLD_MSR_PM, {.hi = 0,.lo = 0x000000005}},
68 struct acpiinit acpi_init_table[] = {
69 {ACPI_IO_BASE + 0x00, 0x01000000},
70 {ACPI_IO_BASE + 0x08, 0},
71 {ACPI_IO_BASE + 0x0C, 0},
72 {ACPI_IO_BASE + 0x1C, 0},
73 {ACPI_IO_BASE + 0x18, 0x0FFFFFFFF},
74 {ACPI_IO_BASE + 0x00, 0x0000FFFF},
75 {PMS_IO_BASE + PM_SCLK, 0x000000E00},
76 {PMS_IO_BASE + PM_SED, 0x000004601},
77 {PMS_IO_BASE + PM_SIDD, 0x000008C02},
78 {PMS_IO_BASE + PM_WKD, 0x0000000A0},
79 {PMS_IO_BASE + PM_WKXD, 0x0000000A0},
84 unsigned char fType; /* Flash type: NOR or NAND */
85 unsigned char fInterface; /* Flash interface: I/O or Memory */
86 unsigned long fMask; /* Flash size/mask */
89 struct FLASH_DEVICE FlashInitTable[] = {
90 {FLASH_TYPE_NAND, FLASH_IF_MEM, FLASH_MEM_4K}, /* CS0, or Flash Device 0 */
91 {FLASH_TYPE_NONE, 0, 0}, /* CS1, or Flash Device 1 */
92 {FLASH_TYPE_NONE, 0, 0}, /* CS2, or Flash Device 2 */
93 {FLASH_TYPE_NONE, 0, 0}, /* CS3, or Flash Device 3 */
96 #define FlashInitTableLen (ARRAY_SIZE(FlashInitTable))
105 /* ***************************************************************************/
109 /* * Program ACPI LBAR and initialize ACPI registers.*/
111 /* ***************************************************************************/
112 static void pmChipsetInit(void)
117 port = (PMS_IO_BASE + 0x010);
118 val = 0x0E00; /* 1ms */
122 /* Make sure bits[3:0]=0000b to clear the */
124 port = (PMS_IO_BASE + 0x034);
125 val = 0x0A0; /* 5ms */
129 port = (PMS_IO_BASE + 0x030);
133 port = (PMS_IO_BASE + 0x014);
134 val = 0x04601; /* 5ms, # of 3.57954MHz clock edges */
138 port = (PMS_IO_BASE + 0x020);
139 val = 0x08C02; /* 10ms, # of 3.57954MHz clock edges */
143 /***************************************************************************
147 * Flash LBARs need to be setup before VSA init so the PCI BARs have
148 * correct size info. Call this routine only if flash needs to be
149 * configured (don't call it if you want IDE).
151 **************************************************************************/
152 static void ChipsetFlashSetup(void)
158 printk(BIOS_DEBUG, "ChipsetFlashSetup: Start\n");
159 for (i = 0; i < FlashInitTableLen; i++) {
160 if (FlashInitTable[i].fType != FLASH_TYPE_NONE) {
161 printk(BIOS_DEBUG, "Enable CS%d\n", i);
162 /* we need to configure the memory/IO mask */
163 msr = rdmsr(FlashPort[i]);
164 msr.hi = 0; /* start with the "enabled" bit clear */
165 if (FlashInitTable[i].fType == FLASH_TYPE_NAND)
166 msr.hi |= 0x00000002;
168 msr.hi &= ~0x00000002;
169 if (FlashInitTable[i].fInterface == FLASH_IF_MEM)
170 msr.hi |= 0x00000004;
172 msr.hi &= ~0x00000004;
173 msr.hi |= FlashInitTable[i].fMask;
174 printk(BIOS_DEBUG, "MSR(0x%08X, %08X_%08X)\n", FlashPort[i],
176 wrmsr(FlashPort[i], msr);
178 /* now write-enable the device */
179 msr = rdmsr(MDD_NORF_CNTRL);
181 printk(BIOS_DEBUG, "MSR(0x%08X, %08X_%08X)\n", MDD_NORF_CNTRL,
183 wrmsr(MDD_NORF_CNTRL, msr);
185 /* update the number enabled */
190 printk(BIOS_DEBUG, "ChipsetFlashSetup: Finish\n");
194 /* ***************************************************************************/
196 /* * enable_ide_nand_flash_header */
197 /* Run after VSA init to enable the flash PCI device header */
199 /* ***************************************************************************/
200 static void enable_ide_nand_flash_header()
202 /* Tell VSA to use FLASH PCI header. Not IDE header. */
203 outl(0x80007A40, 0xCF8);
204 outl(0xDEADBEEF, 0xCFC);
207 #define RTC_CENTURY 0x32
208 #define RTC_DOMA 0x3D
209 #define RTC_MONA 0x3E
211 static void lpc_init(struct southbridge_amd_cs5536_config *sb)
215 if (sb->lpc_serirq_enable) {
216 msr.lo = sb->lpc_serirq_enable;
218 wrmsr(MDD_IRQM_LPC, msr);
219 if (sb->lpc_serirq_polarity) {
220 msr.lo = sb->lpc_serirq_polarity << 16;
221 msr.lo |= (sb->lpc_serirq_mode << 6) | (1 << 7); /* enable */
223 wrmsr(MDD_LPC_SIRQ, msr);
227 /* Allow DMA from LPC */
228 msr = rdmsr(MDD_DMA_MAP);
230 wrmsr(MDD_DMA_MAP, msr);
232 /* enable the RTC/CMOS century byte at address 32h */
233 msr = rdmsr(MDD_RTC_CENTURY_OFFSET);
234 msr.lo = RTC_CENTURY;
235 wrmsr(MDD_RTC_CENTURY_OFFSET, msr);
237 /* enable the RTC/CMOS day of month and month alarms */
238 msr = rdmsr(MDD_RTC_DOMA_IND);
240 wrmsr(MDD_RTC_DOMA_IND, msr);
242 msr = rdmsr(MDD_RTC_MONA_IND);
244 wrmsr(MDD_RTC_MONA_IND, msr);
253 * Depending on settings in the config struct, enable COM1 or COM2 or both.
255 * If the enable is NOT set, the UARTs are explicitly disabled, which is
256 * required if (e.g.) there is a Super I/O attached that does COM1 or COM2.
258 * @param sb Southbridge config structure.
260 static void uarts_init(struct southbridge_amd_cs5536_config *sb)
267 dev = dev_find_device(PCI_VENDOR_ID_AMD,
268 PCI_DEVICE_ID_AMD_CS5536_ISA, 0);
269 gpio_addr = pci_read_config32(dev, PCI_BASE_ADDRESS_1);
270 gpio_addr &= ~1; /* Clear I/O bit */
271 printk(BIOS_DEBUG, "GPIO_ADDR: %08X\n", gpio_addr);
273 /* This could be extended to support IR modes. */
276 if (sb->com1_enable) {
277 printk(BIOS_SPEW, "uarts_init: enable COM1\n");
278 /* Set the address. */
279 switch (sb->com1_address) {
293 msr = rdmsr(MDD_LEG_IO);
294 msr.lo |= addr << 16;
295 wrmsr(MDD_LEG_IO, msr);
298 msr = rdmsr(MDD_IRQM_YHIGH);
299 msr.lo |= sb->com1_irq << 24;
300 wrmsr(MDD_IRQM_YHIGH, msr);
302 /* GPIO8 - UART1_TX */
303 /* Set: Output Enable (0x4) */
304 outl(GPIOL_8_SET, gpio_addr + GPIOL_OUTPUT_ENABLE);
305 /* Set: OUTAUX1 Select (0x10) */
306 outl(GPIOL_8_SET, gpio_addr + GPIOL_OUT_AUX1_SELECT);
308 /* GPIO9 - UART1_RX */
309 /* Set: Input Enable (0x20) */
310 outl(GPIOL_9_SET, gpio_addr + GPIOL_INPUT_ENABLE);
311 /* Set: INAUX1 Select (0x34) */
312 outl(GPIOL_9_SET, gpio_addr + GPIOL_IN_AUX1_SELECT);
314 /* Set: GPIO 8 + 9 Pull Up (0x18) */
315 outl(GPIOL_8_SET | GPIOL_9_SET,
316 gpio_addr + GPIOL_PULLUP_ENABLE);
320 * Bit 1 = device enable
321 * Bit 4 = allow access to the upper banks
323 msr.lo = (1 << 4) | (1 << 1);
325 wrmsr(MDD_UART1_CONF, msr);
327 /* Reset and disable COM1. */
328 printk(BIOS_SPEW, "uarts_init: disable COM1\n");
329 msr = rdmsr(MDD_UART1_CONF);
330 msr.lo = 1; /* Reset */
331 wrmsr(MDD_UART1_CONF, msr);
332 msr.lo = 0; /* Disabled */
333 wrmsr(MDD_UART1_CONF, msr);
335 /* Disable the IRQ. */
336 msr = rdmsr(MDD_LEG_IO);
337 msr.lo &= ~(0xF << 16);
338 wrmsr(MDD_LEG_IO, msr);
342 if (sb->com2_enable) {
343 printk(BIOS_SPEW, "uarts_init: enable COM2\n");
344 switch (sb->com2_address) {
358 msr = rdmsr(MDD_LEG_IO);
359 msr.lo |= addr << 20;
360 wrmsr(MDD_LEG_IO, msr);
361 printk(BIOS_SPEW, "uarts_init: wrote COM2 address 0x%x\n", sb->com2_address);
364 msr = rdmsr(MDD_IRQM_YHIGH);
365 msr.lo |= sb->com2_irq << 28;
366 wrmsr(MDD_IRQM_YHIGH, msr);
367 printk(BIOS_SPEW, "uarts_init: set COM2 irq\n");
369 /* GPIO3 - UART2_RX */
370 /* Set: Input Enable (0x20) */
371 outl(GPIOL_3_SET, gpio_addr + GPIOL_INPUT_ENABLE);
372 /* Set: INAUX1 Select (0x34) */
373 outl(GPIOL_3_SET, gpio_addr + GPIOL_IN_AUX1_SELECT);
375 /* GPIO4 - UART2_TX */
376 /* Set: Output Enable (0x4) */
377 outl(GPIOL_4_SET, gpio_addr + GPIOL_OUTPUT_ENABLE);
378 printk(BIOS_SPEW, "uarts_init: set output enable\n");
379 /* Set: OUTAUX1 Select (0x10) */
380 outl(GPIOL_4_SET, gpio_addr + GPIOL_OUT_AUX1_SELECT);
381 printk(BIOS_SPEW, "uarts_init: set OUTAUX1\n");
383 /* Set: GPIO 3 + 4 Pull Up (0x18) */
384 outl(GPIOL_3_SET | GPIOL_4_SET,
385 gpio_addr + GPIOL_PULLUP_ENABLE);
386 printk(BIOS_SPEW, "uarts_init: set pullup COM2\n");
390 * Bit 1 = device enable
391 * Bit 4 = allow access to the upper banks
393 msr.lo = (1 << 4) | (1 << 1);
395 wrmsr(MDD_UART2_CONF, msr);
396 printk(BIOS_SPEW, "uarts_init: COM2 enabled\n");
398 printk(BIOS_SPEW, "uarts_init: disable COM2\n");
399 /* Reset and disable COM2. */
400 msr = rdmsr(MDD_UART2_CONF);
401 msr.lo = 1; /* Reset */
402 wrmsr(MDD_UART2_CONF, msr);
403 msr.lo = 0; /* Disabled */
404 wrmsr(MDD_UART2_CONF, msr);
406 /* Disable the IRQ. */
407 msr = rdmsr(MDD_LEG_IO);
408 msr.lo &= ~(0xF << 20);
409 wrmsr(MDD_LEG_IO, msr);
414 #define HCCPARAMS 0x08
416 #define USB_HCCPW_SET (1 << 1)
418 #define APU_SET (1 << 15)
420 #define PMUX_HOST 0x02
421 #define PMUX_DEVICE 0x03
422 #define PUEN_SET (1 << 2)
423 #define UDCDEVCTL 0x404
424 #define UDC_SD_SET (1 << 10)
426 #define PADEN_SET (1 << 7)
428 static void enable_USB_port4(struct southbridge_amd_cs5536_config *sb)
434 dev = dev_find_device(PCI_VENDOR_ID_AMD,
435 PCI_DEVICE_ID_AMD_CS5536_EHCI, 0);
438 /* Serial Short Detect Enable */
439 msr = rdmsr(USB2_SB_GLD_MSR_CONF);
440 msr.hi |= USB2_UPPER_SSDEN_SET;
441 wrmsr(USB2_SB_GLD_MSR_CONF, msr);
443 /* write to clear diag register */
444 wrmsr(USB2_SB_GLD_MSR_DIAG, rdmsr(USB2_SB_GLD_MSR_DIAG));
446 bar = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
448 /* Make HCCPARAMS writeable */
449 write32(bar + IPREG04, read32(bar + IPREG04) | USB_HCCPW_SET);
451 /* ; EECP=50h, IST=01h, ASPC=1 */
452 write32(bar + HCCPARAMS, 0x00005012);
455 dev = dev_find_device(PCI_VENDOR_ID_AMD,
456 PCI_DEVICE_ID_AMD_CS5536_OTG, 0);
458 bar = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
460 write32(bar + UOCMUX, read32(bar + UOCMUX) & PUEN_SET);
462 /* Host or Device? */
463 if (sb->enable_USBP4_device) {
464 write32(bar + UOCMUX, read32(bar + UOCMUX) | PMUX_DEVICE);
466 write32(bar + UOCMUX, read32(bar + UOCMUX) | PMUX_HOST);
469 /* Overcurrent configuration */
470 if (sb->enable_USBP4_overcurrent) {
471 write32(bar + UOCCAP, read32(bar + UOCCAP)
472 | sb->enable_USBP4_overcurrent);
476 /* PBz#6466: If the UOC(OTG) device, port 4, is configured as a device,
477 * then perform the following sequence:
479 * - set SD bit in DEVCTRL udc register
480 * - set PADEN (former OTGPADEN) bit in uoc register
481 * - set APU bit in uoc register */
482 if (sb->enable_USBP4_device) {
483 dev = dev_find_device(PCI_VENDOR_ID_AMD,
484 PCI_DEVICE_ID_AMD_CS5536_UDC, 0);
486 bar = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
487 write32(bar + UDCDEVCTL,
488 read32(bar + UDCDEVCTL) | UDC_SD_SET);
492 dev = dev_find_device(PCI_VENDOR_ID_AMD,
493 PCI_DEVICE_ID_AMD_CS5536_OTG, 0);
495 bar = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
496 write32(bar + UOCCTL, read32(bar + UOCCTL) | PADEN_SET);
497 write32(bar + UOCCAP, read32(bar + UOCCAP) | APU_SET);
501 /* Disable virtual PCI UDC and OTG headers */
502 dev = dev_find_device(PCI_VENDOR_ID_AMD,
503 PCI_DEVICE_ID_AMD_CS5536_UDC, 0);
505 pci_write_config32(dev, 0x7C, 0xDEADBEEF);
508 dev = dev_find_device(PCI_VENDOR_ID_AMD,
509 PCI_DEVICE_ID_AMD_CS5536_OTG, 0);
511 pci_write_config32(dev, 0x7C, 0xDEADBEEF);
515 /* ***************************************************************************/
518 /* Called from northbridge init (Pre-VSA). */
520 /* ***************************************************************************/
521 void chipsetinit(void)
526 struct southbridge_amd_cs5536_config *sb =
527 (struct southbridge_amd_cs5536_config *)dev->chip_info;
530 post_code(P80_CHIPSET_INIT);
532 /* we hope NEVER to be in coreboot when S3 resumes
533 if (! IsS3Resume()) */
535 struct acpiinit *aci = acpi_init_table;
536 for (; aci->ioreg; aci++) {
537 outl(aci->regdata, aci->ioreg);
545 outl(GPIOL_2_SET, GPIO_IO_BASE + GPIOL_INPUT_ENABLE);
546 outl(GPIOL_2_SET, GPIO_IO_BASE + GPIOL_IN_AUX1_SELECT);
548 /* Allow IO read and writes during a ATA DMA operation. */
549 /* This could be done in the HD rom but do it here for easier debugging. */
550 msrnum = ATA_SB_GLD_MSR_ERR;
555 /* Enable Post Primary IDE. */
556 msrnum = GLPCI_SB_CTRL;
558 msr.lo |= GLPCI_CRTL_PPIDE_SET;
561 csi = SB_MASTER_CONF_TABLE;
562 for (; csi->msrnum; csi++) {
563 msr.lo = csi->msr.lo;
564 msr.hi = csi->msr.hi;
565 wrmsr(csi->msrnum, msr); // MSR - see table above
568 /* Flash BAR size Setup */
569 printk(BIOS_ERR, "%sDoing ChipsetFlashSetup()\n",
570 sb->enable_ide_nand_flash == 1 ? "" : "Not ");
571 if (sb->enable_ide_nand_flash == 1)
575 /* Set up Hardware Clock Gating */
578 csi = CS5536_CLOCK_GATING_TABLE;
579 for (; csi->msrnum; csi++) {
580 msr.lo = csi->msr.lo;
581 msr.hi = csi->msr.hi;
582 wrmsr(csi->msrnum, msr); // MSR - see table above
587 static void southbridge_init(struct device *dev)
589 struct southbridge_amd_cs5536_config *sb =
590 (struct southbridge_amd_cs5536_config *)dev->chip_info;
593 * struct device *gpiodev;
594 * unsigned short gpiobase = MDD_GPIO;
597 printk(BIOS_ERR, "cs5536: %s\n", __func__);
602 if (sb->enable_gpio_int_route) {
603 vrWrite((VRC_MISCELLANEOUS << 8) + PCI_INT_AB,
604 (sb->enable_gpio_int_route & 0xFFFF));
605 vrWrite((VRC_MISCELLANEOUS << 8) + PCI_INT_CD,
606 (sb->enable_gpio_int_route >> 16));
609 printk(BIOS_ERR, "cs5536: %s: enable_ide_nand_flash is %d\n", __func__,
610 sb->enable_ide_nand_flash);
611 if (sb->enable_ide_nand_flash == 1) {
612 enable_ide_nand_flash_header();
615 enable_USB_port4(sb);
617 /* disable unwanted virtual PCI devices */
618 for (i = 0; (i < MAX_UNWANTED_VPCI) && (0 != sb->unwanted_vpci[i]); i++) {
619 printk(BIOS_DEBUG, "Disabling VPCI device: 0x%08X\n",
620 sb->unwanted_vpci[i]);
621 outl(sb->unwanted_vpci[i] + 0x7C, 0xCF8);
622 outl(0xDEADBEEF, 0xCFC);
626 static void cs5536_read_resources(device_t dev)
628 struct resource *res;
630 pci_dev_read_resources(dev);
632 res = new_resource(dev, 1);
635 res->limit = 0xffffUL;
636 res->flags = IORESOURCE_IO |
637 IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
639 res = new_resource(dev, 3); /* IOAPIC */
640 res->base = 0xfec00000;
641 res->size = 0x00001000;
642 res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
645 static void southbridge_enable(struct device *dev)
647 printk(BIOS_ERR, "cs5536: %s: dev is %p\n", __func__, dev);
651 static void cs5536_pci_dev_enable_resources(device_t dev)
653 printk(BIOS_ERR, "cs5536: %s()\n", __func__);
654 pci_dev_enable_resources(dev);
655 enable_childrens_resources(dev);
658 static struct device_operations southbridge_ops = {
659 .read_resources = cs5536_read_resources,
660 .set_resources = pci_dev_set_resources,
661 .enable_resources = cs5536_pci_dev_enable_resources,
662 .init = southbridge_init,
663 // .enable = southbridge_enable,
664 .scan_bus = scan_static_bus,
667 static const struct pci_driver cs5536_pci_driver __pci_driver = {
668 .ops = &southbridge_ops,
669 .vendor = PCI_VENDOR_ID_AMD,
670 .device = PCI_DEVICE_ID_AMD_CS5536_ISA
673 struct chip_operations southbridge_amd_cs5536_ops = {
674 CHIP_NAME("AMD Geode CS5536 Southbridge")
675 /* This is only called when this device is listed in the
676 * static device tree.
678 .enable_dev = southbridge_enable,