2 * This file is part of the coreboot project.
4 * Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 #ifndef SOUTHBRIDGE_AMD_CS5530_CS5530_H
22 #define SOUTHBRIDGE_AMD_CS5530_CS5530_H
24 #if !defined(__PRE_RAM__)
26 void cs5530_enable(device_t dev);
29 #define DECODE_CONTROL_REG2 0x5b /* F0 index 0x5b */
30 #define ROM_AT_LOGIC_CONTROL_REG 0x52 /* F0 index 0x52 */
32 #define LOWER_ROM_ADDRESS_RANGE (1 << 0)
33 #define ROM_WRITE_ENABLE (1 << 1)
34 #define UPPER_ROM_ADDRESS_RANGE (1 << 2)
35 #define BIOS_ROM_POSITIVE_DECODE (1 << 5)
37 /* Selects PCI positive decoding for accesses to the configured ROM space. */
38 #define BIOS_ROM_POSITIVE_DECODE (1 << 5)
40 /* Primary IDE Controller Positive Decode (i.e., enable it). */
41 #define PRIMARY_IDE_ENABLE (1 << 3)
43 /* Secondary IDE Controller Positive Decode (i.e., enable it). */
44 #define SECONDARY_IDE_ENABLE (1 << 4)
46 #endif /* SOUTHBRIDGE_AMD_CS5530_CS5530_H */