src/southbridge/amd/cimx_wrapper/sb800/late.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2010 Advanced Micro Devices, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  18  */
  19
  20 #include <device/device.h>
  21 #include <device/pci.h>
  22 #include <device/pci_ids.h>
  23 #include <device/smbus.h>
  24 #include <console/console.h>
  25 #include <southbridge/amd/cimx_wrapper/sb800/lpc.h>
  26 #include <southbridge/amd/cimx_wrapper/sb800/SBPLATFORM.h>
  27 #include <southbridge/amd/cimx_wrapper/sb800/cfg.h>
  28 #include "chip.h"
  29
  30 /*implement in mainboard.c*/
  31 //void set_pcie_assert(void);
  32 //void set_pcie_deassert(void);
  33 void set_pcie_reset(void);
  34 void set_pcie_dereset(void);
  35
  36 #ifndef _RAMSTAGE_
  37 #define _RAMSTAGE_
  38 #endif
  39
  40 static AMDSBCFG sb_late_cfg; //global, init in sb800_cimx_config
  41 static AMDSBCFG *sb_config = &sb_late_cfg;
  42
  43 /**
  44  * @brief Entry point of Southbridge CIMx callout
  45  *
  46  * prototype UINT32 (*SBCIM_HOOK_ENTRY)(UINT32 Param1, UINT32 Param2, void* pConfig)
  47  *
  48  * @param[in] func      Southbridge CIMx Function ID.
  49  * @param[in] data      Southbridge Input Data.
  50  * @param[in] sb_config Southbridge configuration structure pointer.
  51  *
  52  */
  53 u32 sb800_callout_entry(u32 func, u32 data, void* config)
  54 {
  55         u32 ret = 0;
  56
  57         switch (func) {
  58         case CB_SBGPP_RESET_ASSERT:
  59                 //set_pcie_assert();
  60                 set_pcie_reset();
  61                 break;
  62
  63         case CB_SBGPP_RESET_DEASSERT:
  64                 //set_pcie_deassert();
  65                 set_pcie_dereset();
  66                 break;
  67
  68         case IMC_FIRMWARE_FAIL:
  69                 break;
  70
  71         default:
  72                 break;
  73         }
  74
  75         return ret;
  76 }
  77
  78 static struct pci_operations lops_pci = {
  79         .set_subsystem = 0,
  80 };
  81
  82 static void lpc_enable_resources(device_t dev)
  83 {
  84         pci_dev_enable_resources(dev);
  85         //lpc_enable_childrens_resources(dev);
  86 }
  87
  88 static void lpc_init(device_t dev)
  89 {
  90         /* SB Configure HPET base and enable bit */
  91         hpetInit(sb_config, &(sb_config->BuildParameters));
  92 }
  93
  94 static struct device_operations lpc_ops = {
  95         .read_resources = lpc_read_resources,
  96         .set_resources = lpc_set_resources,
  97         .enable_resources = lpc_enable_resources,
  98         .init = lpc_init,
  99         .scan_bus = scan_static_bus,
 100         .ops_pci = &lops_pci,
 101 };
 102
 103 static const struct pci_driver lpc_driver __pci_driver = {
 104         .ops = &lpc_ops,
 105         .vendor = PCI_VENDOR_ID_ATI,
 106         .device = PCI_DEVICE_ID_ATI_SB800_LPC,
 107 };
 108
 109 static void sata_enable_resources(struct device *dev)
 110 {
 111         sataInitAfterPciEnum(sb_config);
 112         pci_dev_enable_resources(dev);
 113 }
 114
 115 static void sata_init(struct device *dev)
 116 {
 117         sb_config->StdHeader.Func = SB_MID_POST_INIT;
 118         AmdSbDispatcher(sb_config); //sataInitMidPost only
 119         commonInitLateBoot(sb_config);
 120         sataInitLatePost(sb_config);
 121 }
 122
 123 static struct device_operations sata_ops = {
 124         .read_resources = pci_dev_read_resources,
 125         .set_resources = pci_dev_set_resources,
 126         .enable_resources = sata_enable_resources, //pci_dev_enable_resources,
 127         .init = sata_init,
 128         .scan_bus = 0,
 129         .ops_pci = &lops_pci,
 130 };
 131
 132 static const struct pci_driver sata_driver __pci_driver = {
 133         .ops = &sata_ops,
 134         .vendor = PCI_VENDOR_ID_ATI,
 135         .device = PCI_DEVICE_ID_ATI_SB800_SATA, //SATA IDE Mode 4390
 136 };
 137
 138 #if CONFIG_USBDEBUG
 139 static void usb_set_resources(struct device *dev)
 140 {
 141         struct resource *res;
 142         u32 base;
 143         u32 old_debug;
 144
 145         old_debug = get_ehci_debug();
 146         set_ehci_debug(0);
 147
 148         pci_dev_set_resources(dev);
 149
 150         res = find_resource(dev, 0x10);
 151         set_ehci_debug(old_debug);
 152         if (!res)
 153                 return;
 154         base = res->base;
 155         set_ehci_base(base);
 156         report_resource_stored(dev, res, "");
 157 }
 158 #endif
 159
 160 static void usb_init(struct device *dev)
 161 {
 162         usbInitAfterPciInit(sb_config);
 163         commonInitLateBoot(sb_config);
 164 }
 165
 166 static struct device_operations usb_ops = {
 167         .read_resources = pci_dev_read_resources,
 168 #if CONFIG_USBDEBUG
 169         .set_resources = usb_set_resources,
 170 #else
 171         .set_resources = pci_dev_set_resources,
 172 #endif
 173         .enable_resources = pci_dev_enable_resources,
 174         .init = usb_init,
 175         .scan_bus = 0,
 176         .ops_pci = &lops_pci,
 177 };
 178
 179 /*
 180  * The pci id of usb ctrl 0 and 1 are the same.
 181  */
 182 static const struct pci_driver usb_ohci123_driver __pci_driver = {
 183         .ops = &usb_ops,
 184         .vendor = PCI_VENDOR_ID_ATI,
 185         .device = PCI_DEVICE_ID_ATI_SB800_USB_18_0, /* OHCI-USB1, OHCI-USB2, OHCI-USB3 */
 186 };
 187
 188 static const struct pci_driver usb_ehci123_driver __pci_driver = {
 189         .ops = &usb_ops,
 190         .vendor = PCI_VENDOR_ID_ATI,
 191         .device = PCI_DEVICE_ID_ATI_SB800_USB_18_2, /* EHCI-USB1, EHCI-USB2, EHCI-USB3 */
 192 };
 193
 194 static const struct pci_driver usb_ohci4_driver __pci_driver = {
 195         .ops = &usb_ops,
 196         .vendor = PCI_VENDOR_ID_ATI,
 197         .device = PCI_DEVICE_ID_ATI_SB800_USB_20_5, /* OHCI-USB4 */
 198 };
 199
 200
 201 static void azalia_init(struct device *dev)
 202 {
 203         azaliaInitAfterPciEnum(sb_config); //Detect and configure High Definition Audio
 204 }
 205
 206 static struct device_operations azalia_ops = {
 207         .read_resources = pci_dev_read_resources,
 208         .set_resources = pci_dev_set_resources,
 209         .enable_resources = pci_dev_enable_resources,
 210         .init = azalia_init,
 211         .scan_bus = 0,
 212         .ops_pci = &lops_pci,
 213 };
 214
 215 static const struct pci_driver azalia_driver __pci_driver = {
 216         .ops = &azalia_ops,
 217         .vendor = PCI_VENDOR_ID_ATI,
 218         .device = PCI_DEVICE_ID_ATI_SB800_HDA,
 219 };
 220
 221 static void gec_init(struct device *dev)
 222 {
 223         gecInitAfterPciEnum(sb_config);
 224         gecInitLatePost(sb_config);
 225         printk(BIOS_DEBUG, "gec hda enabled\n");
 226 }
 227
 228 static struct device_operations gec_ops = {
 229         .read_resources = pci_dev_read_resources,
 230         .set_resources = pci_dev_set_resources,
 231         .enable_resources = pci_dev_enable_resources,
 232         .init = gec_init,
 233         .scan_bus = 0,
 234         .ops_pci = &lops_pci,
 235 };
 236
 237 static const struct pci_driver gec_driver __pci_driver = {
 238         .ops = &gec_ops,
 239         .vendor = PCI_VENDOR_ID_ATI,
 240         .device = PCI_DEVICE_ID_ATI_SB800_GEC,
 241 };
 242
 243 static void pcie_init(device_t dev)
 244 {
 245         sbPcieGppLateInit(sb_config);
 246 }
 247
 248 static struct device_operations pci_ops = {
 249         .read_resources = pci_bus_read_resources,
 250         .set_resources = pci_dev_set_resources,
 251         .enable_resources = pci_bus_enable_resources,
 252         .init = pcie_init,
 253         .scan_bus = pci_scan_bridge,
 254         .reset_bus = pci_bus_reset,
 255         .ops_pci = &lops_pci,
 256 };
 257
 258 static const struct pci_driver pci_driver __pci_driver = {
 259         .ops = &pci_ops,
 260         .vendor = PCI_VENDOR_ID_ATI,
 261         .device = PCI_DEVICE_ID_ATI_SB800_PCI,
 262 };
 263
 264 struct device_operations bridge_ops = {
 265         .read_resources   = pci_bus_read_resources,
 266         .set_resources    = pci_dev_set_resources,
 267         .enable_resources = pci_bus_enable_resources,
 268         .init             = pcie_init,
 269         .scan_bus         = pci_scan_bridge,
 270         .enable           = 0,
 271         .reset_bus        = pci_bus_reset,
 272         .ops_pci          = &lops_pci,
 273 };
 274
 275 /* 0:15:0 PCIe PortA */
 276 static const struct pci_driver PORTA_driver __pci_driver = {
 277         .ops = &bridge_ops,
 278         .vendor = PCI_VENDOR_ID_ATI,
 279         .device = PCI_DEVICE_ID_ATI_SB800_PCIEA,
 280 };
 281
 282 /* 0:15:1 PCIe PortB */
 283 static const struct pci_driver PORTB_driver __pci_driver = {
 284         .ops = &bridge_ops,
 285         .vendor = PCI_VENDOR_ID_ATI,
 286         .device = PCI_DEVICE_ID_ATI_SB800_PCIEB,
 287 };
 288
 289 /* 0:15:2 PCIe PortC */
 290 static const struct pci_driver PORTC_driver __pci_driver = {
 291         .ops = &bridge_ops,
 292         .vendor = PCI_VENDOR_ID_ATI,
 293         .device = PCI_DEVICE_ID_ATI_SB800_PCIEC,
 294 };
 295
 296 /* 0:15:3 PCIe PortD */
 297 static const struct pci_driver PORTD_driver __pci_driver = {
 298         .ops = &bridge_ops,
 299         .vendor = PCI_VENDOR_ID_ATI,
 300         .device = PCI_DEVICE_ID_ATI_SB800_PCIED,
 301 };
 302
 303 /**
 304  * @brief SB Cimx entry point sbBeforePciInit wrapper
 305  */
 306 static void sb800_enable(device_t dev)
 307 {
 308         u8 gpp_port = 0;
 309         struct southbridge_amd_cimx_wrapper_sb800_config *sb_chip =
 310                 (struct southbridge_amd_cimx_wrapper_sb800_config *)(dev->chip_info);
 311
 312         sb800_cimx_config(sb_config);
 313         printk(BIOS_DEBUG, "sb800_enable() ");
 314
 315         /* Config SouthBridge SMBUS/ACPI/IDE/LPC/PCIB.*/
 316         commonInitEarlyBoot(sb_config);
 317         commonInitEarlyPost(sb_config);
 318
 319         switch (dev->path.pci.devfn) {
 320         case (0x11 << 3) | 0: /* 0:11.0  SATA */
 321                 if (dev->enabled) {
 322                         sb_config->SATAMODE.SataMode.SataController = ENABLED;
 323                         if (1 == sb_chip->boot_switch_sata_ide)
 324                                 sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = 0; //0 -IDE as primary.
 325                         else if (0 == sb_chip->boot_switch_sata_ide)
 326                                 sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = 1; //1 -IDE as secondary.
 327                 } else {
 328                         sb_config->SATAMODE.SataMode.SataController = DISABLED;
 329                 }
 330
 331                 sataInitBeforePciEnum(sb_config); // Init SATA class code and PHY
 332                 break;
 333
 334         case (0x12 << 3) | 0: /* 0:12:0 OHCI-USB1 */
 335         case (0x12 << 3) | 2: /* 0:12:2 EHCI-USB1 */
 336         case (0x13 << 3) | 0: /* 0:13:0 OHCI-USB2 */
 337         case (0x13 << 3) | 2: /* 0:13:2 EHCI-USB2 */
 338         case (0x14 << 3) | 5: /* 0:14:5 OHCI-USB4 */
 339         case (0x16 << 3) | 0: /* 0:16:0 OHCI-USB3 */
 340         case (0x16 << 3) | 2: /* 0:16:2 EHCI-USB3 */
 341                 usbInitBeforePciEnum(sb_config);  // USB POST TIME Only
 342                 break;
 343
 344         case (0x14 << 3) | 0: /* 0:14:0 SMBUS */
 345                 break;
 346
 347         case (0x14 << 3) | 1: /* 0:14:1 IDE */
 348                 if (dev->enabled) {
 349                         sb_config->SATAMODE.SataMode.SataIdeCombinedMode = ENABLED;
 350                 } else {
 351                         sb_config->SATAMODE.SataMode.SataIdeCombinedMode = DISABLED;
 352                 }
 353                 sataInitBeforePciEnum(sb_config); // Init SATA class code and PHY
 354                 break;
 355
 356         case (0x14 << 3) | 2: /* 0:14:2 HDA */
 357                 if (dev->enabled) {
 358                         if (AZALIA_DISABLE == sb_config->AzaliaController) {
 359                                 sb_config->AzaliaController = AZALIA_AUTO;
 360                         }
 361                         printk(BIOS_DEBUG, "hda enabled\n");
 362                 } else {
 363                         sb_config->AzaliaController = AZALIA_DISABLE;
 364                         printk(BIOS_DEBUG, "hda disabled\n");
 365                 }
 366                 azaliaInitBeforePciEnum(sb_config); // Detect and configure High Definition Audio
 367                 break;
 368
 369
 370         case (0x14 << 3) | 3: /* 0:14:3 LPC */
 371                 break;
 372
 373         case (0x14 << 3) | 4: /* 0:14:4 PCI */
 374                 break;
 375
 376         case (0x14 << 3) | 6: /* 0:14:6 GEC */
 377                 if (dev->enabled) {
 378                         sb_config->GecConfig = 0;
 379                         printk(BIOS_DEBUG, "gec enabled\n");
 380                 } else {
 381                         sb_config->GecConfig = 1;
 382                         printk(BIOS_DEBUG, "gec disabled\n");
 383                 }
 384                 gecInitBeforePciEnum(sb_config); // Init GEC
 385                 break;
 386
 387         case (0x15 << 3) | 0: /* 0:15:0 PCIe PortA */
 388         case (0x15 << 3) | 1: /* 0:15:1 PCIe PortB */
 389         case (0x15 << 3) | 2: /* 0:15:2 PCIe PortC */
 390         case (0x15 << 3) | 3: /* 0:15:3 PCIe PortD */
 391                 gpp_port = (dev->path.pci.devfn) & 0x03;
 392                 if (dev->enabled) {
 393                         sb_config->PORTCONFIG[gpp_port].PortCfg.PortPresent = ENABLED;
 394                 } else {
 395                         sb_config->PORTCONFIG[gpp_port].PortCfg.PortPresent = DISABLED;
 396                 }
 397
 398                 /*
 399                  * GPP_CFGMODE_X4000: PortA Lanes[3:0]
 400                  * GPP_CFGMODE_X2200: PortA Lanes[1:0], PortB Lanes[3:2]
 401                  * GPP_CFGMODE_X2110: PortA Lanes[1:0], PortB Lane2, PortC Lane3
 402                  * GPP_CFGMODE_X1111: PortA Lanes0, PortB Lane1, PortC Lane2, PortD Lane3
 403                  */
 404                 if (sb_config->GppLinkConfig != sb_chip->gpp_configuration) {
 405                         sb_config->GppLinkConfig = sb_chip->gpp_configuration;
 406                 }
 407
 408                 sbPcieGppEarlyInit(sb_config);
 409                 break;
 410
 411         default:
 412                 break;
 413         }
 414
 415         /* Special setting ABCFG registers before PCI emulation. */
 416         abSpecialSetBeforePciEnum(sb_config);
 417         usbDesertPll(sb_config);
 418         //sb_config->StdHeader.Func = SB_BEFORE_PCI_INIT;
 419         //AmdSbDispatcher(sb_config);
 420 }
 421
 422 struct chip_operations southbridge_amd_cimx_wrapper_sb800_ops = {
 423         CHIP_NAME("ATI SB800")
 424         .enable_dev = sb800_enable,
 425 };