2 *****************************************************************************
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4 * This file is part of the coreboot project.
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6 * Copyright (C) 2010 Advanced Micro Devices, Inc.
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8 * This program is free software; you can redistribute it and/or modify
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9 * it under the terms of the GNU General Public License as published by
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10 * the Free Software Foundation; version 2 of the License.
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12 * This program is distributed in the hope that it will be useful,
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13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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15 * GNU General Public License for more details.
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17 * You should have received a copy of the GNU General Public License
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18 * along with this program; if not, write to the Free Software
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19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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20 * ***************************************************************************
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24 #ifndef _AMD_SBPLATFORM_H_
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25 #define _AMD_SBPLATFORM_H_
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27 #include <southbridge/amd/cimx_wrapper/sb800/cbtypes.h>
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28 typedef UINT64 PLACEHOLDER;
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29 #include <southbridge/amd/cimx_wrapper/sb800/Amdlib.h>
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30 #include <southbridge/amd/cimx_wrapper/sb800/Amd.h>
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31 #include <vendorcode/amd/cimx/lib/amdlib32.h> //TODO merge with agesa wrapper
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32 #include <vendorcode/amd/cimx/sb800/SB800.h>
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33 #include <vendorcode/amd/cimx/sb800/SBTYPE.h>
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34 #include <vendorcode/amd/cimx/sb800/ACPILIB.h>
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35 #include <vendorcode/amd/cimx/sb800/SBDEF.h>
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36 #include <vendorcode/amd/cimx/sb800/AMDSBLIB.h>
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37 #include <vendorcode/amd/cimx/sb800/SBSUBFUN.h>
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38 #include <vendorcode/amd/cimx/sb800/OEM.h>
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45 #ifndef SBOEM_ACPI_RESTORE_SWSMI
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46 #define SBOEM_BEFORE_PCI_RESTORE_SWSMI 0xD3
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47 #define SBOEM_AFTER_PCI_RESTORE_SWSMI 0xD4
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50 #ifndef _AMD_NB_CIM_X_PROTOCOL_H_
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52 /// Extended PCI Address
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53 typedef struct _EXT_PCI_ADDR {
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54 UINT32 Reg :16; ///< / PCI Register
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55 UINT32 Func:3; ///< / PCI Function
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56 UINT32 Dev :5; ///< / PCI Device
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57 UINT32 Bus :8; ///< / PCI Address
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61 typedef union _PCI_ADDR {
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62 UINT32 ADDR; ///< / 32 bit Address
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63 EXT_PCI_ADDR Addr; ///< / Extended PCI Address
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67 #define FIXUP_PTR(ptr) ptr
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69 //------------------------------------------------------------------------------------------------------------------------//
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71 * SB_CIMx_PARAMETER 0 1 2 Defult Value When CIMx Take over
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72 * SpreadSpectrum CIMx take over User (Setup Option) User (Setup Option) Enable
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73 * SpreadSpectrumType CIMx take over User (Setup Option) User (Setup Option) Normal
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74 * HpetTimer CIMx take over User (Setup Option) User (Setup Option) Enable
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75 * HpetMsiDis CIMx take over User (Setup Option) User (Setup Option) Enable (0x00)
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76 * IrConfig CIMx take over User (Setup Option) User (Setup Option) Disable (0x00)
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77 * SpiFastReadEnable CIMx take over User (Setup Option) User (Setup Option) Disable
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78 * SpiFastReadSpeed CIMx take over User (Setup Option) User (Setup Option) Disable (NULL)
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79 * NbSbGen2 CIMx take over User (Setup Option) User (Setup Option) Enable
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80 * AlinkPhyPllPowerDown CIMx take over User (Setup Option) User (Setup Option) Enable
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81 * ResetCpuOnSyncFlood CIMx take over User (Setup Option) User (Setup Option) Enable
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82 * GppGen2 CIMx take over User (Setup Option) User (Setup Option) Disable
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83 * GppMemWrImprove CIMx take over User (Setup Option) User (Setup Option) Enable
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84 * GppPortAspm CIMx take over User (Setup Option) User (Setup Option) Disable
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85 * GppLaneReversal CIMx take over User (Setup Option) User (Setup Option) Disable
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86 * GppPhyPllPowerDown CIMx take over User (Setup Option) User (Setup Option) Enable
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87 * UsbPhyPowerDown CIMx take over User (Setup Option) User (Setup Option) Disable
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88 * SBGecDebugBus CIMx take over User (Setup Option) User (Setup Option) Disable
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89 * SBGecPwr CIMx take over User (Setup Option) User (Setup Option) Nerver Power down (0x11)
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90 * SataSetMaxGen2 CIMx take over User (Setup Option) User (Setup Option) Max Gen3 (0x00)
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91 * SataClkMode CIMx take over User (Setup Option) User (Setup Option) 0x90 int. 100Mhz
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92 * SataAggrLinkPmCap CIMx take over User (Setup Option) User (Setup Option) Enable
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93 * SataPortMultCap CIMx take over User (Setup Option) User (Setup Option) Enable
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94 * SataPscCap CIMx take over User (Setup Option) User (Setup Option) Enable (0x00)
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95 * SataSscCap CIMx take over User (Setup Option) User (Setup Option) Enable (0x00)
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96 * SataFisBasedSwitching CIMx take over User (Setup Option) User (Setup Option) Disable
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97 * SataCccSupport CIMx take over User (Setup Option) User (Setup Option) Disable
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98 * SataMsiCapability CIMx take over User (Setup Option) User (Setup Option) Enable
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99 * SataClkAutoOff CIMx take over User (Setup Option) User (Setup Option) Disable
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100 * AcDcMsg CIMx take over User (Setup Option) User (Setup Option) Disable
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101 * TimerTickTrack CIMx take over User (Setup Option) User (Setup Option) Disable
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102 * ClockInterruptTag CIMx take over User (Setup Option) User (Setup Option) Disable
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103 * OhciTrafficHanding CIMx take over User (Setup Option) User (Setup Option) Disable
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104 * EhciTrafficHanding CIMx take over User (Setup Option) User (Setup Option) Disable
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105 * FusionMsgCMultiCore CIMx take over User (Setup Option) User (Setup Option) Disable
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106 * FusionMsgCStage CIMx take over User (Setup Option) User (Setup Option) Disable
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108 #define SB_CIMx_PARAMETER 0x02
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111 #define cimSpreadSpectrumDefault TRUE
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112 #define cimSpreadSpectrumTypeDefault 0x00 // Normal
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113 #define cimHpetTimerDefault TRUE
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114 #define cimHpetMsiDisDefault FALSE // Enable
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115 #define cimIrConfigDefault 0x00 // Disable
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116 #define cimSpiFastReadEnableDefault 0x00 // Disable
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117 #define cimSpiFastReadSpeedDefault 0x00 // NULL
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118 // GPP/AB Controller
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119 #define cimNbSbGen2Default TRUE
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120 #define cimAlinkPhyPllPowerDownDefault TRUE
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121 #define cimResetCpuOnSyncFloodDefault TRUE
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122 #define cimGppGen2Default FALSE
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123 #define cimGppMemWrImproveDefault TRUE
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124 #define cimGppPortAspmDefault FALSE
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125 #define cimGppLaneReversalDefault FALSE
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126 #define cimGppPhyPllPowerDownDefault TRUE
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128 #define cimUsbPhyPowerDownDefault FALSE
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130 #define cimSBGecDebugBusDefault FALSE
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131 #define cimSBGecPwrDefault 0x03
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132 // Sata Controller
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133 #define cimSataSetMaxGen2Default 0x00
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134 #define cimSATARefClkSelDefault 0x10
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135 #define cimSATARefDivSelDefault 0x80
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136 #define cimSataAggrLinkPmCapDefault TRUE
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137 #define cimSataPortMultCapDefault TRUE
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138 #define cimSataPscCapDefault 0x00 // Enable
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139 #define cimSataSscCapDefault 0x00 // Enable
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140 #define cimSataFisBasedSwitchingDefault FALSE
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141 #define cimSataCccSupportDefault FALSE
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142 #define cimSataClkAutoOffDefault FALSE
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143 #define cimNativepciesupportDefault FALSE
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145 #define cimAcDcMsgDefault FALSE
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146 #define cimTimerTickTrackDefault FALSE
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147 #define cimClockInterruptTagDefault FALSE
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148 #define cimOhciTrafficHandingDefault FALSE
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149 #define cimEhciTrafficHandingDefault FALSE
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150 #define cimFusionMsgCMultiCoreDefault FALSE
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151 #define cimFusionMsgCStageDefault FALSE
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153 #endif // _AMD_SBPLATFORM_H_
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