2 *****************************************************************************
4 * This file is part of the coreboot project.
6 * Copyright (C) 2010 Advanced Micro Devices, Inc.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 * ***************************************************************************
24 #ifndef _AMD_SBPLATFORM_H_
25 #define _AMD_SBPLATFORM_H_
27 #include <southbridge/amd/cimx_wrapper/sb800/cbtypes.h>
28 typedef UINT64 PLACEHOLDER;
29 #include <southbridge/amd/cimx_wrapper/sb800/Amdlib.h>
30 #include <southbridge/amd/cimx_wrapper/sb800/Amd.h>
31 #include <vendorcode/amd/cimx/lib/amdlib32.h> //TODO merge with agesa wrapper
32 #include <vendorcode/amd/cimx/sb800/SB800.h>
33 #include <vendorcode/amd/cimx/sb800/SBTYPE.h>
34 #include <vendorcode/amd/cimx/sb800/ACPILIB.h>
35 #include <vendorcode/amd/cimx/sb800/SBDEF.h>
36 #include <vendorcode/amd/cimx/sb800/AMDSBLIB.h>
37 #include <vendorcode/amd/cimx/sb800/SBSUBFUN.h>
38 #include <vendorcode/amd/cimx/sb800/OEM.h>
45 #ifndef SBOEM_ACPI_RESTORE_SWSMI
46 #define SBOEM_BEFORE_PCI_RESTORE_SWSMI 0xD3
47 #define SBOEM_AFTER_PCI_RESTORE_SWSMI 0xD4
50 #ifndef _AMD_NB_CIM_X_PROTOCOL_H_
52 /// Extended PCI Address
53 typedef struct _EXT_PCI_ADDR {
54 UINT32 Reg :16; ///< / PCI Register
55 UINT32 Func:3; ///< / PCI Function
56 UINT32 Dev :5; ///< / PCI Device
57 UINT32 Bus :8; ///< / PCI Address
61 typedef union _PCI_ADDR {
62 UINT32 ADDR; ///< / 32 bit Address
63 EXT_PCI_ADDR Addr; ///< / Extended PCI Address
67 #define FIXUP_PTR(ptr) ptr
69 //------------------------------------------------------------------------------------------------------------------------//
71 * SB_CIMx_PARAMETER 0 1 2 Defult Value When CIMx Take over
72 * SpreadSpectrum CIMx take over User (Setup Option) User (Setup Option) Enable
73 * SpreadSpectrumType CIMx take over User (Setup Option) User (Setup Option) Normal
74 * HpetTimer CIMx take over User (Setup Option) User (Setup Option) Enable
75 * HpetMsiDis CIMx take over User (Setup Option) User (Setup Option) Enable (0x00)
76 * IrConfig CIMx take over User (Setup Option) User (Setup Option) Disable (0x00)
77 * SpiFastReadEnable CIMx take over User (Setup Option) User (Setup Option) Disable
78 * SpiFastReadSpeed CIMx take over User (Setup Option) User (Setup Option) Disable (NULL)
79 * NbSbGen2 CIMx take over User (Setup Option) User (Setup Option) Enable
80 * AlinkPhyPllPowerDown CIMx take over User (Setup Option) User (Setup Option) Enable
81 * ResetCpuOnSyncFlood CIMx take over User (Setup Option) User (Setup Option) Enable
82 * GppGen2 CIMx take over User (Setup Option) User (Setup Option) Disable
83 * GppMemWrImprove CIMx take over User (Setup Option) User (Setup Option) Enable
84 * GppPortAspm CIMx take over User (Setup Option) User (Setup Option) Disable
85 * GppLaneReversal CIMx take over User (Setup Option) User (Setup Option) Disable
86 * GppPhyPllPowerDown CIMx take over User (Setup Option) User (Setup Option) Enable
87 * UsbPhyPowerDown CIMx take over User (Setup Option) User (Setup Option) Disable
88 * SBGecDebugBus CIMx take over User (Setup Option) User (Setup Option) Disable
89 * SBGecPwr CIMx take over User (Setup Option) User (Setup Option) Nerver Power down (0x11)
90 * SataSetMaxGen2 CIMx take over User (Setup Option) User (Setup Option) Max Gen3 (0x00)
91 * SataClkMode CIMx take over User (Setup Option) User (Setup Option) 0x90 int. 100Mhz
92 * SataAggrLinkPmCap CIMx take over User (Setup Option) User (Setup Option) Enable
93 * SataPortMultCap CIMx take over User (Setup Option) User (Setup Option) Enable
94 * SataPscCap CIMx take over User (Setup Option) User (Setup Option) Enable (0x00)
95 * SataSscCap CIMx take over User (Setup Option) User (Setup Option) Enable (0x00)
96 * SataFisBasedSwitching CIMx take over User (Setup Option) User (Setup Option) Disable
97 * SataCccSupport CIMx take over User (Setup Option) User (Setup Option) Disable
98 * SataMsiCapability CIMx take over User (Setup Option) User (Setup Option) Enable
99 * SataClkAutoOff CIMx take over User (Setup Option) User (Setup Option) Disable
100 * AcDcMsg CIMx take over User (Setup Option) User (Setup Option) Disable
101 * TimerTickTrack CIMx take over User (Setup Option) User (Setup Option) Disable
102 * ClockInterruptTag CIMx take over User (Setup Option) User (Setup Option) Disable
103 * OhciTrafficHanding CIMx take over User (Setup Option) User (Setup Option) Disable
104 * EhciTrafficHanding CIMx take over User (Setup Option) User (Setup Option) Disable
105 * FusionMsgCMultiCore CIMx take over User (Setup Option) User (Setup Option) Disable
106 * FusionMsgCStage CIMx take over User (Setup Option) User (Setup Option) Disable
108 #define SB_CIMx_PARAMETER 0x02
111 #define cimSpreadSpectrumDefault TRUE
112 #define cimSpreadSpectrumTypeDefault 0x00 // Normal
113 #define cimHpetTimerDefault TRUE
114 #define cimHpetMsiDisDefault FALSE // Enable
115 #define cimIrConfigDefault 0x00 // Disable
116 #define cimSpiFastReadEnableDefault 0x00 // Disable
117 #define cimSpiFastReadSpeedDefault 0x00 // NULL
119 #define cimNbSbGen2Default TRUE
120 #define cimAlinkPhyPllPowerDownDefault TRUE
121 #define cimResetCpuOnSyncFloodDefault TRUE
122 #define cimGppGen2Default FALSE
123 #define cimGppMemWrImproveDefault TRUE
124 #define cimGppPortAspmDefault FALSE
125 #define cimGppLaneReversalDefault FALSE
126 #define cimGppPhyPllPowerDownDefault TRUE
128 #define cimUsbPhyPowerDownDefault FALSE
130 #define cimSBGecDebugBusDefault FALSE
131 #define cimSBGecPwrDefault 0x03
133 #define cimSataSetMaxGen2Default 0x00
134 #define cimSATARefClkSelDefault 0x10
135 #define cimSATARefDivSelDefault 0x80
136 #define cimSataAggrLinkPmCapDefault TRUE
137 #define cimSataPortMultCapDefault TRUE
138 #define cimSataPscCapDefault 0x00 // Enable
139 #define cimSataSscCapDefault 0x00 // Enable
140 #define cimSataFisBasedSwitchingDefault FALSE
141 #define cimSataCccSupportDefault FALSE
142 #define cimSataClkAutoOffDefault FALSE
143 #define cimNativepciesupportDefault FALSE
145 #define cimAcDcMsgDefault FALSE
146 #define cimTimerTickTrackDefault FALSE
147 #define cimClockInterruptTagDefault FALSE
148 #define cimOhciTrafficHandingDefault FALSE
149 #define cimEhciTrafficHandingDefault FALSE
150 #define cimFusionMsgCMultiCoreDefault FALSE
151 #define cimFusionMsgCStageDefault FALSE
153 #endif // _AMD_SBPLATFORM_H_