src/southbridge/amd/cimx/sb800/late.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2011 Advanced Micro Devices, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  18  */
  19
  20
  21 #include <device/device.h>      /* device_t */
  22 #include <device/pci.h>         /* device_operations */
  23 #include <device/pci_ids.h>
  24 #include <arch/ioapic.h>
  25 #include <device/smbus.h>       /* smbus_bus_operations */
  26 #include <console/console.h>    /* printk */
  27 #include "lpc.h"                /* lpc_read_resources */
  28 #include "SBPLATFORM.h"         /* Platfrom Specific Definitions */
  29 #include "cfg.h"                /* sb800 Cimx configuration */
  30 #include "chip.h"               /* struct southbridge_amd_cimx_sb800_config */
  31 #include "sb_cimx.h"            /* AMD CIMX wrapper entries */
  32
  33
  34 /*implement in mainboard.c*/
  35 void set_pcie_reset(void);
  36 void set_pcie_dereset(void);
  37
  38
  39 static AMDSBCFG sb_late_cfg; //global, init in sb800_cimx_config
  40 static AMDSBCFG *sb_config = &sb_late_cfg;
  41
  42
  43 /**
  44  * @brief Entry point of Southbridge CIMx callout
  45  *
  46  * prototype UINT32 (*SBCIM_HOOK_ENTRY)(UINT32 Param1, UINT32 Param2, void* pConfig)
  47  *
  48  * @param[in] func      Southbridge CIMx Function ID.
  49  * @param[in] data      Southbridge Input Data.
  50  * @param[in] sb_config Southbridge configuration structure pointer.
  51  *
  52  */
  53 u32 sb800_callout_entry(u32 func, u32 data, void* config)
  54 {
  55         u32 ret = 0;
  56         printk(BIOS_DEBUG, "SB800 - Late.c - %s - Start.\n", __func__);
  57         switch (func) {
  58         case CB_SBGPP_RESET_ASSERT:
  59                 set_pcie_reset();
  60                 break;
  61
  62         case CB_SBGPP_RESET_DEASSERT:
  63                 set_pcie_dereset();
  64                 break;
  65
  66         case IMC_FIRMWARE_FAIL:
  67                 break;
  68
  69         default:
  70                 break;
  71         }
  72
  73         printk(BIOS_DEBUG, "SB800 - Late.c - %s - End.\n", __func__);
  74         return ret;
  75 }
  76
  77 #define HOST_CAP                  0x00 /* host capabilities */
  78 #define HOST_CTL                  0x04 /* global host control */
  79 #define HOST_IRQ_STAT             0x08 /* interrupt status */
  80 #define HOST_PORTS_IMPL           0x0c /* bitmap of implemented ports */
  81
  82 #define HOST_CTL_AHCI_EN          (1 << 31) /* AHCI enabled */
  83 static void ahci_raid_init(struct device *dev)
  84 {
  85         u8 irq = 0;
  86         u32 bar5, caps, ports, val;
  87
  88         val = pci_read_config16(dev, PCI_CLASS_DEVICE);
  89         if (val == PCI_CLASS_STORAGE_SATA) {
  90                 printk(BIOS_DEBUG, "AHCI controller ");
  91         } else if (val == PCI_CLASS_STORAGE_RAID) {
  92                 printk(BIOS_DEBUG, "RAID controller ");
  93         } else {
  94                 printk(BIOS_WARNING, "device class:%x, neither in ahci or raid mode\n", val);
  95                 return;
  96         }
  97
  98         irq = pci_read_config8(dev, PCI_INTERRUPT_LINE);
  99         bar5 = pci_read_config32(dev, PCI_BASE_ADDRESS_5);
 100         printk(BIOS_DEBUG, "IOMEM base: 0x%X, IRQ: 0x%X\n", bar5, irq);
 101
 102         caps = *(volatile u32 *)(bar5 + HOST_CAP);
 103         caps = (caps & 0x1F) + 1;
 104         ports= *(volatile u32 *)(bar5 + HOST_PORTS_IMPL);
 105         printk(BIOS_DEBUG, "Number of Ports: 0x%x, Port implemented(bit map): 0x%x\n", caps, ports);
 106
 107         /* make sure ahci is enabled */
 108         val = *(volatile u32 *)(bar5 + HOST_CTL);
 109         if (!(val & HOST_CTL_AHCI_EN)) {
 110                 *(volatile u32 *)(bar5 + HOST_CTL) = val | HOST_CTL_AHCI_EN;
 111         }
 112
 113         dev->command |= PCI_COMMAND_MASTER;
 114         pci_write_config8(dev, PCI_COMMAND, dev->command);
 115         printk(BIOS_DEBUG, "AHCI/RAID controller initialized\n");
 116 }
 117
 118 static struct pci_operations lops_pci = {
 119         .set_subsystem = pci_dev_set_subsystem,
 120 };
 121
 122 static struct device_operations lpc_ops = {
 123         .read_resources = lpc_read_resources,
 124         .set_resources = lpc_set_resources,
 125         .enable_resources = pci_dev_enable_resources,
 126         .init = 0,
 127         .scan_bus = scan_static_bus,
 128         .ops_pci = &lops_pci,
 129 };
 130
 131 static const struct pci_driver lpc_driver __pci_driver = {
 132         .ops = &lpc_ops,
 133         .vendor = PCI_VENDOR_ID_ATI,
 134         .device = PCI_DEVICE_ID_ATI_SB800_LPC,
 135 };
 136
 137 static struct device_operations sata_ops = {
 138         .read_resources = pci_dev_read_resources,
 139         .set_resources = pci_dev_set_resources,
 140         .enable_resources = pci_dev_enable_resources,
 141         .init = ahci_raid_init,
 142         .scan_bus = 0,
 143         .ops_pci = &lops_pci,
 144 };
 145
 146 static const struct pci_driver ahci_driver __pci_driver = {
 147         .ops = &sata_ops,
 148         .vendor = PCI_VENDOR_ID_ATI,
 149         .device = PCI_DEVICE_ID_ATI_SB800_SATA_AHCI,
 150 };
 151
 152 static const struct pci_driver raid_driver __pci_driver = {
 153         .ops = &sata_ops,
 154         .vendor = PCI_VENDOR_ID_ATI,
 155         .device = PCI_DEVICE_ID_ATI_SB800_SATA_RAID,
 156 };
 157 static const struct pci_driver raid5_driver __pci_driver = {
 158         .ops = &sata_ops,
 159         .vendor = PCI_VENDOR_ID_ATI,
 160         .device = PCI_DEVICE_ID_ATI_SB800_SATA_RAID5,
 161 };
 162
 163 #if CONFIG_USBDEBUG == 1
 164 static void usb_set_resources(struct device *dev)
 165 {
 166         struct resource *res;
 167         u32 base;
 168         u32 old_debug;
 169
 170         printk(BIOS_DEBUG, "SB800 - Late.c - %s - Start.\n", __func__);
 171         old_debug = get_ehci_debug();
 172         set_ehci_debug(0);
 173
 174         pci_dev_set_resources(dev);
 175
 176         res = find_resource(dev, 0x10);
 177         set_ehci_debug(old_debug);
 178         if (!res)
 179                 return;
 180         base = res->base;
 181         set_ehci_base(base);
 182         report_resource_stored(dev, res, "");
 183         printk(BIOS_DEBUG, "SB800 - Late.c - %s - End.\n", __func__);
 184 }
 185 #endif
 186
 187 static struct device_operations usb_ops = {
 188         .read_resources = pci_dev_read_resources,
 189 #if CONFIG_USBDEBUG
 190         .set_resources = usb_set_resources,
 191 #else
 192         .set_resources = pci_dev_set_resources,
 193 #endif
 194         .enable_resources = pci_dev_enable_resources,
 195         .init = 0,
 196         .scan_bus = 0,
 197         .ops_pci = &lops_pci,
 198 };
 199
 200 /*
 201  * The pci id of usb ctrl 0 and 1 are the same.
 202  */
 203 static const struct pci_driver usb_ohci123_driver __pci_driver = {
 204         .ops = &usb_ops,
 205         .vendor = PCI_VENDOR_ID_ATI,
 206         .device = PCI_DEVICE_ID_ATI_SB800_USB_18_0, /* OHCI-USB1, OHCI-USB2, OHCI-USB3 */
 207 };
 208
 209 static const struct pci_driver usb_ehci123_driver __pci_driver = {
 210         .ops = &usb_ops,
 211         .vendor = PCI_VENDOR_ID_ATI,
 212         .device = PCI_DEVICE_ID_ATI_SB800_USB_18_2, /* EHCI-USB1, EHCI-USB2, EHCI-USB3 */
 213 };
 214
 215 static const struct pci_driver usb_ohci4_driver __pci_driver = {
 216         .ops = &usb_ops,
 217         .vendor = PCI_VENDOR_ID_ATI,
 218         .device = PCI_DEVICE_ID_ATI_SB800_USB_20_5, /* OHCI-USB4 */
 219 };
 220
 221
 222 static struct device_operations azalia_ops = {
 223         .read_resources = pci_dev_read_resources,
 224         .set_resources = pci_dev_set_resources,
 225         .enable_resources = pci_dev_enable_resources,
 226         .init = 0,
 227         .scan_bus = 0,
 228         .ops_pci = &lops_pci,
 229 };
 230
 231 static const struct pci_driver azalia_driver __pci_driver = {
 232         .ops = &azalia_ops,
 233         .vendor = PCI_VENDOR_ID_ATI,
 234         .device = PCI_DEVICE_ID_ATI_SB800_HDA,
 235 };
 236
 237
 238 static struct device_operations gec_ops = {
 239         .read_resources = pci_dev_read_resources,
 240         .set_resources = pci_dev_set_resources,
 241         .enable_resources = pci_dev_enable_resources,
 242         .init = 0,
 243         .scan_bus = 0,
 244         .ops_pci = &lops_pci,
 245 };
 246
 247 static const struct pci_driver gec_driver __pci_driver = {
 248         .ops = &gec_ops,
 249         .vendor = PCI_VENDOR_ID_ATI,
 250         .device = PCI_DEVICE_ID_ATI_SB800_GEC,
 251 };
 252
 253 /**
 254  * @brief Enable PCI Bridge
 255  *
 256  * PcibConfig [PM_Reg: EAh], PCIDisable [Bit0]
 257  * 'PCIDisable' set to 0 to enable P2P bridge.
 258  * 'PCIDisable' set to 1 to disable P2P bridge and enable PCI interface pins
 259  *              to function as GPIO {GPIO 35:0}.
 260  */
 261 static void pci_init(device_t dev)
 262 {
 263         /* PCI Bridge SHOULD be enabled by default according to SB800 rrg,
 264          * but actually was disabled in some platform, so I have to enabled it.
 265          */
 266         RWMEM(ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEA, AccWidthUint8, ~BIT0, 0);
 267 }
 268
 269
 270 static struct device_operations pci_ops = {
 271         .read_resources = pci_bus_read_resources,
 272         .set_resources = pci_dev_set_resources,
 273         .enable_resources = pci_bus_enable_resources,
 274         .init = pci_init,
 275         .scan_bus = pci_scan_bridge,
 276         .reset_bus = pci_bus_reset,
 277         .ops_pci = &lops_pci,
 278 };
 279
 280 static const struct pci_driver pci_driver __pci_driver = {
 281         .ops = &pci_ops,
 282         .vendor = PCI_VENDOR_ID_ATI,
 283         .device = PCI_DEVICE_ID_ATI_SB800_PCI,
 284 };
 285
 286
 287 struct device_operations bridge_ops = {
 288         .read_resources   = pci_bus_read_resources,
 289         .set_resources    = pci_dev_set_resources,
 290         .enable_resources = pci_bus_enable_resources,
 291         .init             = 0,
 292         .scan_bus         = pci_scan_bridge,
 293         .enable           = 0,
 294         .reset_bus        = pci_bus_reset,
 295         .ops_pci          = &lops_pci,
 296 };
 297
 298 /* 0:15:0 PCIe PortA */
 299 static const struct pci_driver PORTA_driver __pci_driver = {
 300         .ops = &bridge_ops,
 301         .vendor = PCI_VENDOR_ID_ATI,
 302         .device = PCI_DEVICE_ID_ATI_SB800_PCIEA,
 303 };
 304
 305 /* 0:15:1 PCIe PortB */
 306 static const struct pci_driver PORTB_driver __pci_driver = {
 307         .ops = &bridge_ops,
 308         .vendor = PCI_VENDOR_ID_ATI,
 309         .device = PCI_DEVICE_ID_ATI_SB800_PCIEB,
 310 };
 311
 312 /* 0:15:2 PCIe PortC */
 313 static const struct pci_driver PORTC_driver __pci_driver = {
 314         .ops = &bridge_ops,
 315         .vendor = PCI_VENDOR_ID_ATI,
 316         .device = PCI_DEVICE_ID_ATI_SB800_PCIEC,
 317 };
 318
 319 /* 0:15:3 PCIe PortD */
 320 static const struct pci_driver PORTD_driver __pci_driver = {
 321         .ops = &bridge_ops,
 322         .vendor = PCI_VENDOR_ID_ATI,
 323         .device = PCI_DEVICE_ID_ATI_SB800_PCIED,
 324 };
 325
 326
 327 /**
 328  * South Bridge CIMx ramstage entry point wrapper.
 329  */
 330 void sb_Before_Pci_Init(void)
 331 {
 332         sb_config->StdHeader.Func = SB_BEFORE_PCI_INIT;
 333         AmdSbDispatcher(sb_config);
 334 }
 335
 336 void sb_After_Pci_Init(void)
 337 {
 338         sb_config->StdHeader.Func = SB_AFTER_PCI_INIT;
 339         AmdSbDispatcher(sb_config);
 340 }
 341
 342 void sb_Mid_Post_Init(void)
 343 {
 344         sb_config->StdHeader.Func = SB_MID_POST_INIT;
 345         AmdSbDispatcher(sb_config);
 346 }
 347
 348 void sb_Late_Post(void)
 349 {
 350         sb_config->StdHeader.Func = SB_LATE_POST_INIT;
 351         AmdSbDispatcher(sb_config);
 352 }
 353
 354
 355 /**
 356  * @brief SB Cimx entry point sbBeforePciInit wrapper
 357  */
 358 static void sb800_enable(device_t dev)
 359 {
 360         struct southbridge_amd_cimx_sb800_config *sb_chip =
 361                 (struct southbridge_amd_cimx_sb800_config *)(dev->chip_info);
 362
 363         printk(BIOS_DEBUG, "sb800_enable() ");
 364
 365         switch (dev->path.pci.devfn) {
 366         case (0x11 << 3) | 0: /* 0:11.0  SATA */
 367                 /* the first sb800 device */
 368                 sb800_cimx_config(sb_config);
 369
 370                 if (dev->enabled) {
 371                         sb_config->SATAMODE.SataMode.SataController = CIMX_OPTION_ENABLED;
 372                         if (1 == sb_chip->boot_switch_sata_ide)
 373                                 sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = 0; //0 -IDE as primary.
 374                         else if (0 == sb_chip->boot_switch_sata_ide)
 375                                 sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = 1; //1 -IDE as secondary.
 376                 } else {
 377                         sb_config->SATAMODE.SataMode.SataController = CIMX_OPTION_DISABLED;
 378                 }
 379                 break;
 380
 381         case (0x14 << 3) | 0: /* 0:14:0 SMBUS */
 382                 printk(BIOS_INFO, "sm_init().\n");
 383                 clear_ioapic(IO_APIC_ADDR);
 384                 /* I/O APIC IDs are normally limited to 4-bits. Enforce this limit. */
 385 #if (CONFIG_APIC_ID_OFFSET == 0 && CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS < 16)
 386                 /* Assign the ioapic ID the next available number after the processor core local APIC IDs */
 387                 setup_ioapic(IO_APIC_ADDR, CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS);
 388 #elif (CONFIG_APIC_ID_OFFSET > 0)
 389                 /* Assign the ioapic ID the value 0. Processor APIC IDs follow. */
 390                 setup_ioapic(IO_APIC_ADDR, 0);
 391 #else
 392 #error "The processor APIC IDs must be lifted to make room for the I/O APIC ID"
 393 #endif
 394                 break;
 395
 396         case (0x14 << 3) | 1: /* 0:14:1 IDE */
 397                 break;
 398
 399         case (0x14 << 3) | 2: /* 0:14:2 HDA */
 400                 if (dev->enabled) {
 401                         if (AZALIA_DISABLE == sb_config->AzaliaController) {
 402                                 sb_config->AzaliaController = AZALIA_AUTO;
 403                         }
 404                         printk(BIOS_DEBUG, "hda enabled\n");
 405                 } else {
 406                         sb_config->AzaliaController = AZALIA_DISABLE;
 407                         printk(BIOS_DEBUG, "hda disabled\n");
 408                 }
 409                 break;
 410
 411
 412         case (0x14 << 3) | 3: /* 0:14:3 LPC */
 413                 break;
 414
 415         case (0x14 << 3) | 4: /* 0:14:4 PCI */
 416                 break;
 417
 418         case (0x14 << 3) | 6: /* 0:14:6 GEC */
 419                 if (dev->enabled) {
 420                         sb_config->GecConfig = 0;
 421                         printk(BIOS_DEBUG, "gec enabled\n");
 422                 } else {
 423                         sb_config->GecConfig = 1;
 424                         printk(BIOS_DEBUG, "gec disabled\n");
 425                 }
 426                 break;
 427
 428         case (0x15 << 3) | 0: /* 0:15:0 PCIe PortA */
 429                 {
 430                         device_t device;
 431                         for (device = dev; device; device = device->next) {
 432                                 if (dev->path.type != DEVICE_PATH_PCI) continue;
 433                                 if ((device->path.pci.devfn & ~7) != PCI_DEVFN(0x15,0)) break;
 434                                 sb_config->PORTCONFIG[device->path.pci.devfn & 3].PortCfg.PortPresent = device->enabled;
 435                         }
 436
 437                         /*
 438                          * GPP_CFGMODE_X4000: PortA Lanes[3:0]
 439                          * GPP_CFGMODE_X2200: PortA Lanes[1:0], PortB Lanes[3:2]
 440                          * GPP_CFGMODE_X2110: PortA Lanes[1:0], PortB Lane2, PortC Lane3
 441                          * GPP_CFGMODE_X1111: PortA Lanes0, PortB Lane1, PortC Lane2, PortD Lane3
 442                          */
 443                         sb_config->GppLinkConfig = sb_chip->gpp_configuration;
 444                 }
 445                 break;
 446
 447         case (0x12 << 3) | 0: /* 0:12:0 OHCI-USB1 */
 448                 sb_config->USBMODE.UsbMode.Ohci1 = dev->enabled;
 449                 break;
 450         case (0x12 << 3) | 2: /* 0:12:2 EHCI-USB1 */
 451                 sb_config->USBMODE.UsbMode.Ehci1 = dev->enabled;
 452                 break;
 453         case (0x13 << 3) | 0: /* 0:13:0 OHCI-USB2 */
 454                 sb_config->USBMODE.UsbMode.Ohci2 = dev->enabled;
 455                 break;
 456         case (0x13 << 3) | 2: /* 0:13:2 EHCI-USB2 */
 457                 sb_config->USBMODE.UsbMode.Ehci2 = dev->enabled;
 458                 break;
 459         case (0x14 << 3) | 5: /* 0:14:5 OHCI-USB4 */
 460                 sb_config->USBMODE.UsbMode.Ohci4 = dev->enabled;
 461                 break;
 462         case (0x16 << 3) | 0: /* 0:16:0 OHCI-USB3 */
 463                 sb_config->USBMODE.UsbMode.Ohci3 = dev->enabled;
 464                 break;
 465         case (0x16 << 3) | 2: /* 0:16:2 EHCI-USB3 */
 466                 sb_config->USBMODE.UsbMode.Ehci3 = dev->enabled;
 467
 468                 /* call the CIMX entry at the last sb800 device,
 469                  * so make sure the mainboard devicetree is complete
 470                  */
 471                 sb_Before_Pci_Init();
 472                 break;
 473
 474         default:
 475                 break;
 476         }
 477 }
 478
 479 struct chip_operations southbridge_amd_cimx_sb800_ops = {
 480         CHIP_NAME("ATI SB800")
 481         .enable_dev = sb800_enable,
 482 };