2 * This file is part of the coreboot project.
4 * Copyright (C) 2011 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 #include <device/device.h> /* device_t */
22 #include <device/pci.h> /* device_operations */
23 #include <device/pci_ids.h>
24 #include <arch/ioapic.h>
25 #include <device/smbus.h> /* smbus_bus_operations */
26 #include <console/console.h> /* printk */
27 #include "lpc.h" /* lpc_read_resources */
28 #include "SBPLATFORM.h" /* Platfrom Specific Definitions */
29 #include "cfg.h" /* sb800 Cimx configuration */
30 #include "chip.h" /* struct southbridge_amd_cimx_sb800_config */
33 /*implement in mainboard.c*/
34 //void set_pcie_assert(void);
35 //void set_pcie_deassert(void);
36 void set_pcie_reset(void);
37 void set_pcie_dereset(void);
43 static AMDSBCFG sb_late_cfg; //global, init in sb800_cimx_config
44 static AMDSBCFG *sb_config = &sb_late_cfg;
48 * @brief Entry point of Southbridge CIMx callout
50 * prototype UINT32 (*SBCIM_HOOK_ENTRY)(UINT32 Param1, UINT32 Param2, void* pConfig)
52 * @param[in] func Southbridge CIMx Function ID.
53 * @param[in] data Southbridge Input Data.
54 * @param[in] sb_config Southbridge configuration structure pointer.
57 u32 sb800_callout_entry(u32 func, u32 data, void* config)
62 case CB_SBGPP_RESET_ASSERT:
67 case CB_SBGPP_RESET_DEASSERT:
68 //set_pcie_deassert();
72 case IMC_FIRMWARE_FAIL:
83 static struct pci_operations lops_pci = {
87 static void lpc_enable_resources(device_t dev)
90 pci_dev_enable_resources(dev);
91 //lpc_enable_childrens_resources(dev);
94 static void lpc_init(device_t dev)
96 /* SB Configure HPET base and enable bit */
97 hpetInit(sb_config, &(sb_config->BuildParameters));
100 static struct device_operations lpc_ops = {
101 .read_resources = lpc_read_resources,
102 .set_resources = lpc_set_resources,
103 .enable_resources = lpc_enable_resources,
105 .scan_bus = scan_static_bus,
106 .ops_pci = &lops_pci,
109 static const struct pci_driver lpc_driver __pci_driver = {
111 .vendor = PCI_VENDOR_ID_ATI,
112 .device = PCI_DEVICE_ID_ATI_SB800_LPC,
116 static void sata_enable_resources(struct device *dev)
118 sataInitAfterPciEnum(sb_config);
119 pci_dev_enable_resources(dev);
122 static void sata_init(struct device *dev)
124 sb_config->StdHeader.Func = SB_MID_POST_INIT;
125 AmdSbDispatcher(sb_config); //sataInitMidPost only
126 commonInitLateBoot(sb_config);
127 sataInitLatePost(sb_config);
130 static struct device_operations sata_ops = {
131 .read_resources = pci_dev_read_resources,
132 .set_resources = pci_dev_set_resources,
133 .enable_resources = sata_enable_resources, //pci_dev_enable_resources,
136 .ops_pci = &lops_pci,
139 static const struct pci_driver sata_driver __pci_driver = {
141 .vendor = PCI_VENDOR_ID_ATI,
142 .device = PCI_DEVICE_ID_ATI_SB800_SATA_AHCI,
146 static void usb_set_resources(struct device *dev)
148 struct resource *res;
152 old_debug = get_ehci_debug();
155 pci_dev_set_resources(dev);
157 res = find_resource(dev, 0x10);
158 set_ehci_debug(old_debug);
163 report_resource_stored(dev, res, "");
167 static void usb_init(struct device *dev)
169 usbInitAfterPciInit(sb_config);
170 commonInitLateBoot(sb_config);
173 static struct device_operations usb_ops = {
174 .read_resources = pci_dev_read_resources,
176 .set_resources = usb_set_resources,
178 .set_resources = pci_dev_set_resources,
180 .enable_resources = pci_dev_enable_resources,
183 .ops_pci = &lops_pci,
187 * The pci id of usb ctrl 0 and 1 are the same.
189 static const struct pci_driver usb_ohci123_driver __pci_driver = {
191 .vendor = PCI_VENDOR_ID_ATI,
192 .device = PCI_DEVICE_ID_ATI_SB800_USB_18_0, /* OHCI-USB1, OHCI-USB2, OHCI-USB3 */
195 static const struct pci_driver usb_ehci123_driver __pci_driver = {
197 .vendor = PCI_VENDOR_ID_ATI,
198 .device = PCI_DEVICE_ID_ATI_SB800_USB_18_2, /* EHCI-USB1, EHCI-USB2, EHCI-USB3 */
201 static const struct pci_driver usb_ohci4_driver __pci_driver = {
203 .vendor = PCI_VENDOR_ID_ATI,
204 .device = PCI_DEVICE_ID_ATI_SB800_USB_20_5, /* OHCI-USB4 */
208 static void azalia_init(struct device *dev)
210 azaliaInitAfterPciEnum(sb_config); //Detect and configure High Definition Audio
213 static struct device_operations azalia_ops = {
214 .read_resources = pci_dev_read_resources,
215 .set_resources = pci_dev_set_resources,
216 .enable_resources = pci_dev_enable_resources,
219 .ops_pci = &lops_pci,
222 static const struct pci_driver azalia_driver __pci_driver = {
224 .vendor = PCI_VENDOR_ID_ATI,
225 .device = PCI_DEVICE_ID_ATI_SB800_HDA,
229 static void gec_init(struct device *dev)
231 gecInitAfterPciEnum(sb_config);
232 gecInitLatePost(sb_config);
233 printk(BIOS_DEBUG, "gec hda enabled\n");
236 static struct device_operations gec_ops = {
237 .read_resources = pci_dev_read_resources,
238 .set_resources = pci_dev_set_resources,
239 .enable_resources = pci_dev_enable_resources,
242 .ops_pci = &lops_pci,
245 static const struct pci_driver gec_driver __pci_driver = {
247 .vendor = PCI_VENDOR_ID_ATI,
248 .device = PCI_DEVICE_ID_ATI_SB800_GEC,
252 static void pcie_init(device_t dev)
254 sbPcieGppLateInit(sb_config);
257 static struct device_operations pci_ops = {
258 .read_resources = pci_bus_read_resources,
259 .set_resources = pci_dev_set_resources,
260 .enable_resources = pci_bus_enable_resources,
262 .scan_bus = pci_scan_bridge,
263 .reset_bus = pci_bus_reset,
264 .ops_pci = &lops_pci,
267 static const struct pci_driver pci_driver __pci_driver = {
269 .vendor = PCI_VENDOR_ID_ATI,
270 .device = PCI_DEVICE_ID_ATI_SB800_PCI,
274 struct device_operations bridge_ops = {
275 .read_resources = pci_bus_read_resources,
276 .set_resources = pci_dev_set_resources,
277 .enable_resources = pci_bus_enable_resources,
279 .scan_bus = pci_scan_bridge,
281 .reset_bus = pci_bus_reset,
282 .ops_pci = &lops_pci,
285 /* 0:15:0 PCIe PortA */
286 static const struct pci_driver PORTA_driver __pci_driver = {
288 .vendor = PCI_VENDOR_ID_ATI,
289 .device = PCI_DEVICE_ID_ATI_SB800_PCIEA,
292 /* 0:15:1 PCIe PortB */
293 static const struct pci_driver PORTB_driver __pci_driver = {
295 .vendor = PCI_VENDOR_ID_ATI,
296 .device = PCI_DEVICE_ID_ATI_SB800_PCIEB,
299 /* 0:15:2 PCIe PortC */
300 static const struct pci_driver PORTC_driver __pci_driver = {
302 .vendor = PCI_VENDOR_ID_ATI,
303 .device = PCI_DEVICE_ID_ATI_SB800_PCIEC,
306 /* 0:15:3 PCIe PortD */
307 static const struct pci_driver PORTD_driver __pci_driver = {
309 .vendor = PCI_VENDOR_ID_ATI,
310 .device = PCI_DEVICE_ID_ATI_SB800_PCIED,
315 * @brief SB Cimx entry point sbBeforePciInit wrapper
317 static void sb800_enable(device_t dev)
319 struct southbridge_amd_cimx_sb800_config *sb_chip =
320 (struct southbridge_amd_cimx_sb800_config *)(dev->chip_info);
322 sb800_cimx_config(sb_config);
323 printk(BIOS_DEBUG, "sb800_enable() ");
325 /* Config SouthBridge SMBUS/ACPI/IDE/LPC/PCIB.*/
326 commonInitEarlyBoot(sb_config);
327 commonInitEarlyPost(sb_config);
329 switch (dev->path.pci.devfn) {
330 case (0x11 << 3) | 0: /* 0:11.0 SATA */
332 sb_config->SATAMODE.SataMode.SataController = CIMX_OPTION_ENABLED;
333 if (1 == sb_chip->boot_switch_sata_ide)
334 sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = 0; //0 -IDE as primary.
335 else if (0 == sb_chip->boot_switch_sata_ide)
336 sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = 1; //1 -IDE as secondary.
338 sb_config->SATAMODE.SataMode.SataController = CIMX_OPTION_DISABLED;
341 sataInitBeforePciEnum(sb_config); // Init SATA class code and PHY
344 case (0x12 << 3) | 0: /* 0:12:0 OHCI-USB1 */
345 case (0x12 << 3) | 2: /* 0:12:2 EHCI-USB1 */
346 case (0x13 << 3) | 0: /* 0:13:0 OHCI-USB2 */
347 case (0x13 << 3) | 2: /* 0:13:2 EHCI-USB2 */
348 case (0x14 << 3) | 5: /* 0:14:5 OHCI-USB4 */
349 case (0x16 << 3) | 0: /* 0:16:0 OHCI-USB3 */
350 case (0x16 << 3) | 2: /* 0:16:2 EHCI-USB3 */
351 usbInitBeforePciEnum(sb_config); // USB POST TIME Only
354 case (0x14 << 3) | 0: /* 0:14:0 SMBUS */
358 printk(BIOS_INFO, "sm_init().\n");
359 ioapic_base = IO_APIC_ADDR;
360 clear_ioapic(ioapic_base);
361 /* I/O APIC IDs are normally limited to 4-bits. Enforce this limit. */
362 #if (CONFIG_APIC_ID_OFFSET == 0 && CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS < 16)
363 /* Assign the ioapic ID the next available number after the processor core local APIC IDs */
364 setup_ioapic(ioapic_base, CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS);
365 #elif (CONFIG_APIC_ID_OFFSET > 0)
366 /* Assign the ioapic ID the value 0. Processor APIC IDs follow. */
367 setup_ioapic(ioapic_base, 0);
369 #error "The processor APIC IDs must be lifted to make room for the I/O APIC ID"
375 case (0x14 << 3) | 1: /* 0:14:1 IDE */
377 sb_config->SATAMODE.SataMode.SataIdeCombinedMode = CIMX_OPTION_ENABLED;
379 sb_config->SATAMODE.SataMode.SataIdeCombinedMode = CIMX_OPTION_DISABLED;
381 sataInitBeforePciEnum(sb_config); // Init SATA class code and PHY
384 case (0x14 << 3) | 2: /* 0:14:2 HDA */
386 if (AZALIA_DISABLE == sb_config->AzaliaController) {
387 sb_config->AzaliaController = AZALIA_AUTO;
389 printk(BIOS_DEBUG, "hda enabled\n");
391 sb_config->AzaliaController = AZALIA_DISABLE;
392 printk(BIOS_DEBUG, "hda disabled\n");
394 azaliaInitBeforePciEnum(sb_config); // Detect and configure High Definition Audio
398 case (0x14 << 3) | 3: /* 0:14:3 LPC */
401 case (0x14 << 3) | 4: /* 0:14:4 PCI */
404 case (0x14 << 3) | 6: /* 0:14:6 GEC */
406 sb_config->GecConfig = 0;
407 printk(BIOS_DEBUG, "gec enabled\n");
409 sb_config->GecConfig = 1;
410 printk(BIOS_DEBUG, "gec disabled\n");
412 gecInitBeforePciEnum(sb_config); // Init GEC
415 case (0x15 << 3) | 0: /* 0:15:0 PCIe PortA */
418 for (device = dev; device; device = device->next) {
419 if (dev->path.type != DEVICE_PATH_PCI) continue;
420 if ((device->path.pci.devfn & ~7) != PCI_DEVFN(0x15,0)) break;
421 sb_config->PORTCONFIG[device->path.pci.devfn & 3].PortCfg.PortPresent = device->enabled;
425 * GPP_CFGMODE_X4000: PortA Lanes[3:0]
426 * GPP_CFGMODE_X2200: PortA Lanes[1:0], PortB Lanes[3:2]
427 * GPP_CFGMODE_X2110: PortA Lanes[1:0], PortB Lane2, PortC Lane3
428 * GPP_CFGMODE_X1111: PortA Lanes0, PortB Lane1, PortC Lane2, PortD Lane3
430 sb_config->GppLinkConfig = sb_chip->gpp_configuration;
431 sb_config->StdHeader.Func = SB_BEFORE_PCI_INIT;
432 AmdSbDispatcher(sb_config);
442 struct chip_operations southbridge_amd_cimx_sb800_ops = {
443 CHIP_NAME("ATI SB800")
444 .enable_dev = sb800_enable,