src/southbridge/amd/cimx/sb700/late.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2012 Advanced Micro Devices, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  18  */
  19
  20
  21 #include <device/device.h>      /* device_t */
  22 #include <device/pci.h>         /* device_operations */
  23 #include <device/pci_ids.h>
  24 #include <arch/ioapic.h>
  25 #include <device/smbus.h>       /* smbus_bus_operations */
  26 #include <console/console.h>    /* printk */
  27 #include "lpc.h"                /* lpc_read_resources */
  28 #include "Platform.h"   /* Platfrom Specific Definitions */
  29 #include "sb_cimx.h"
  30 #include "sb700_cfg.h"                /* sb700 Cimx configuration */
  31 #include "chip.h"               /* struct southbridge_amd_cimx_sb700_config */
  32
  33
  34 /*implement in mainboard.c*/
  35 void set_pcie_reset(void);
  36 void set_pcie_dereset(void);
  37
  38 static AMDSBCFG sb_late_cfg; //global, init in sb700_cimx_config
  39 static AMDSBCFG *sb_config = &sb_late_cfg;
  40
  41
  42 /**
  43  * @brief Entry point of Southbridge CIMx callout
  44  *
  45  * prototype UINT32 (*SBCIM_HOOK_ENTRY)(UINT32 Param1, UINT32 Param2, void* pConfig)
  46  *
  47  * @param[in] func      Southbridge CIMx Function ID.
  48  * @param[in] data      Southbridge Input Data.
  49  * @param[in] sb_config Southbridge configuration structure pointer.
  50  *
  51  */
  52 u32 sb700_callout_entry(u32 func, u32 data, void* config)
  53 {
  54         u32 ret = 0;
  55
  56         printk(BIOS_DEBUG, "SB700 - Late.c - sb700_callout_entry - Start.\n");
  57         printk(BIOS_DEBUG, "SB700 - Late.c - sb700_callout_entry - End.\n");
  58         return ret;
  59 }
  60
  61
  62 static struct pci_operations lops_pci = {
  63         .set_subsystem = pci_dev_set_subsystem,
  64 };
  65
  66 static void lpc_enable_resources(device_t dev)
  67 {
  68
  69         printk(BIOS_SPEW, "SB700 - Late.c - %s - Start.\n", __func__);
  70         pci_dev_enable_resources(dev);
  71         lpc_enable_childrens_resources(dev);
  72         printk(BIOS_SPEW, "SB700 - Late.c - %s - End.\n", __func__);
  73 }
  74
  75 static struct device_operations lpc_ops = {
  76         .read_resources = lpc_read_resources,
  77         .set_resources = lpc_set_resources,
  78         .enable_resources = lpc_enable_resources,
  79         .init = 0,
  80         .scan_bus = scan_static_bus,
  81         .ops_pci = &lops_pci,
  82 };
  83
  84 static const struct pci_driver lpc_driver __pci_driver = {
  85         .ops = &lpc_ops,
  86         .vendor = PCI_VENDOR_ID_ATI,
  87         .device = PCI_DEVICE_ID_ATI_SB700_LPC,
  88 };
  89
  90
  91 static struct device_operations sata_ops = {
  92         .read_resources = pci_dev_read_resources,
  93         .set_resources = pci_dev_set_resources,
  94         .enable_resources = pci_dev_enable_resources,
  95         .init = 0,
  96         .scan_bus = 0,
  97         .ops_pci = &lops_pci,
  98 };
  99
 100 static const struct pci_driver sata_driver __pci_driver = {
 101         .ops = &sata_ops,
 102         .vendor = PCI_VENDOR_ID_ATI,
 103         .device = PCI_DEVICE_ID_ATI_SB700_SATA, //SATA IDE Mode 4390
 104 };
 105
 106 #if CONFIG_USBDEBUG
 107 static void usb_set_resources(struct device *dev)
 108 {
 109         struct resource *res;
 110         u32 base;
 111         u32 old_debug;
 112
 113         printk(BIOS_SPEW, "SB700 - Late.c - %s - Start.\n", __func__);
 114         old_debug = get_ehci_debug();
 115         set_ehci_debug(0);
 116
 117         pci_dev_set_resources(dev);
 118
 119         res = find_resource(dev, 0x10);
 120         set_ehci_debug(old_debug);
 121         if (!res)
 122                 return;
 123         base = res->base;
 124         set_ehci_base(base);
 125         report_resource_stored(dev, res, "");
 126         printk(BIOS_SPEW, "SB700 - Late.c - %s - End.\n", __func__);
 127 }
 128 #endif
 129
 130
 131 static struct device_operations usb_ops = {
 132         .read_resources = pci_dev_read_resources,
 133 #if CONFIG_USBDEBUG
 134         .set_resources = usb_set_resources,
 135 #else
 136         .set_resources = pci_dev_set_resources,
 137 #endif
 138         .enable_resources = pci_dev_enable_resources,
 139         .init = 0,
 140         .scan_bus = 0,
 141         .ops_pci = &lops_pci,
 142 };
 143
 144 /*
 145  * The pci id of usb ctrl 0 and 1 are the same.
 146  */
 147 static const struct pci_driver usb_ohci123_driver __pci_driver = {
 148         .ops = &usb_ops,
 149         .vendor = PCI_VENDOR_ID_ATI,
 150         .device = PCI_DEVICE_ID_ATI_SB700_USB_18_0, /* OHCI-USB1, OHCI-USB2, OHCI-USB3 */
 151 };
 152
 153 static const struct pci_driver usb_ohci3_driver __pci_driver = {
 154         .ops = &usb_ops,
 155         .vendor = PCI_VENDOR_ID_ATI,
 156         .device = PCI_DEVICE_ID_ATI_SB700_USB_18_1,
 157 };
 158
 159 static const struct pci_driver usb_ehci123_driver __pci_driver = {
 160         .ops = &usb_ops,
 161         .vendor = PCI_VENDOR_ID_ATI,
 162         .device = PCI_DEVICE_ID_ATI_SB700_USB_18_2, /* EHCI-USB1, EHCI-USB2, EHCI-USB3 */
 163 };
 164
 165 static const struct pci_driver usb_ohci4_driver __pci_driver = {
 166         .ops = &usb_ops,
 167         .vendor = PCI_VENDOR_ID_ATI,
 168         .device = PCI_DEVICE_ID_ATI_SB700_USB_20_5, /* OHCI-USB4 */
 169 };
 170
 171 static struct device_operations azalia_ops = {
 172         .read_resources = pci_dev_read_resources,
 173         .set_resources = pci_dev_set_resources,
 174         .enable_resources = pci_dev_enable_resources,
 175         .init = 0,
 176         .scan_bus = 0,
 177         .ops_pci = &lops_pci,
 178 };
 179
 180 static const struct pci_driver azalia_driver __pci_driver = {
 181         .ops = &azalia_ops,
 182         .vendor = PCI_VENDOR_ID_ATI,
 183         .device = PCI_DEVICE_ID_ATI_SB700_HDA,
 184 };
 185
 186
 187 static struct device_operations pci_ops = {
 188         .read_resources = pci_bus_read_resources,
 189         .set_resources = pci_dev_set_resources,
 190         .enable_resources = pci_bus_enable_resources,
 191         .init = 0,
 192         .scan_bus = pci_scan_bridge,
 193         .reset_bus = pci_bus_reset,
 194         .ops_pci = &lops_pci,
 195 };
 196
 197 static const struct pci_driver pci_driver __pci_driver = {
 198         .ops = &pci_ops,
 199         .vendor = PCI_VENDOR_ID_ATI,
 200         .device = PCI_DEVICE_ID_ATI_SB700_PCI,
 201 };
 202
 203
 204 static void sb700_enable(device_t dev)
 205 {
 206         struct southbridge_amd_cimx_sb700_config *sb_chip =
 207                 (struct southbridge_amd_cimx_sb700_config *)(dev->chip_info);
 208
 209         printk(BIOS_DEBUG, "sb700_enable() ");
 210         switch (dev->path.pci.devfn) {
 211                 case (0x11 << 3) | 0: /* 0:11.0  SATA */
 212                         sb700_cimx_config(sb_config);
 213                         if (dev->enabled) {
 214                                 sb_config->SataController = CIMX_OPTION_ENABLED;
 215                                 if (1 == sb_chip->boot_switch_sata_ide)
 216                                         sb_config->SataIdeCombMdPriSecOpt = 0; //0 -IDE as primary.
 217                                 else if (0 == sb_chip->boot_switch_sata_ide)
 218                                         sb_config->SataIdeCombMdPriSecOpt = 1; //1 -IDE as secondary.
 219                         } else {
 220                                 sb_config->SataController = CIMX_OPTION_DISABLED;
 221                         }
 222                         break;
 223
 224                 case (0x12 << 3) | 0: /* 0:12:0 OHCI-USB1 */
 225                 case (0x12 << 3) | 2: /* 0:12:2 EHCI-USB1 */
 226                 case (0x13 << 3) | 0: /* 0:13:0 OHCI-USB2 */
 227                 case (0x13 << 3) | 2: /* 0:13:2 EHCI-USB2 */
 228                         break;
 229
 230                 case (0x14 << 3) | 0: /* 0:14:0 SMBUS */
 231                         {
 232 #if 1
 233                                 u32 ioapic_base;
 234                                 printk(BIOS_DEBUG, "sm_init().\n");
 235                                 ioapic_base = IO_APIC_ADDR;
 236                                 clear_ioapic(ioapic_base);
 237                                 /* I/O APIC IDs are normally limited to 4-bits. Enforce this limit. */
 238 #if (CONFIG_APIC_ID_OFFSET == 0 && CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS >= 1)
 239                                 /* Assign the ioapic ID the next available number after the processor core local APIC IDs */
 240                                 setup_ioapic(ioapic_base, CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS);
 241 #elif (CONFIG_APIC_ID_OFFSET > 0)
 242                                 /* Assign the ioapic ID the value 0. Processor APIC IDs follow. */
 243                                 setup_ioapic(ioapic_base, 0);
 244 #else
 245 #error "The processor APIC IDs must be lifted to make room for the I/O APIC ID"
 246 #endif
 247 #endif
 248                         }
 249                         break;
 250
 251                 case (0x14 << 3) | 1: /* 0:14:1 IDE */
 252                         break;
 253
 254                 case (0x14 << 3) | 2: /* 0:14:2 HDA */
 255                         if (dev->enabled) {
 256                                 if (AZALIA_DISABLE == sb_config->AzaliaController) {
 257                                         sb_config->AzaliaController = AZALIA_AUTO;
 258                                 }
 259                                 printk(BIOS_DEBUG, "hda enabled\n");
 260                         } else {
 261                                 sb_config->AzaliaController = AZALIA_DISABLE;
 262                                 printk(BIOS_DEBUG, "hda disabled\n");
 263                         }
 264                         break;
 265
 266
 267                 case (0x14 << 3) | 3: /* 0:14:3 LPC */
 268                         break;
 269
 270                 case (0x14 << 3) | 4: /* 0:14:4 PCI */
 271                         break;
 272
 273                 case (0x14 << 3) | 5: /* 0:14:5 OHCI-USB4 */
 274                         /* call CIMX entry after last device enable */
 275                         sb_Before_Pci_Init();
 276                         break;
 277
 278                 default:
 279                         break;
 280         }
 281 }
 282
 283 struct chip_operations southbridge_amd_cimx_sb700_ops = {
 284         CHIP_NAME("ATI SB700")
 285         .enable_dev = sb700_enable,
 286 };
 287
 288 /**
 289  * @brief SB Cimx entry point sbBeforePciInit wrapper
 290  */
 291 void sb_Before_Pci_Init(void)
 292 {
 293         printk(BIOS_SPEW, "sb700 %s Start\n", __func__);
 294         /* TODO: The sb700 cimx dispatcher not work yet, calling cimx API directly */
 295         //sb_config->StdHeader.Func = SB_BEFORE_PCI_INIT;
 296         //AmdSbDispatcher(sb_config);
 297         sbBeforePciInit(sb_config);
 298         printk(BIOS_SPEW, "sb700 %s End\n", __func__);
 299 }
 300
 301 void sb_After_Pci_Init(void)
 302 {
 303         printk(BIOS_SPEW, "sb700 %s Start\n", __func__);
 304         /* TODO: The sb700 cimx dispatcher not work yet, calling cimx API directly */
 305         //sb_config->StdHeader.Func = SB_AFTER_PCI_INIT;
 306         //AmdSbDispatcher(sb_config);
 307         sbAfterPciInit(sb_config);
 308         printk(BIOS_SPEW, "sb700 %s End\n", __func__);
 309 }
 310
 311 void sb_Late_Post(void)
 312 {
 313         printk(BIOS_SPEW, "sb700 %s Start\n", __func__);
 314         /* TODO: The sb700 cimx dispatcher not work yet, calling cimx API directly */
 315         //sb_config->StdHeader.Func = SB_LATE_POST_INIT;
 316         //AmdSbDispatcher(sb_config);
 317         sbLatePost(sb_config);
 318         printk(BIOS_SPEW, "sb700 %s End\n", __func__);
 319 }