src/southbridge/amd/amd8131-disable/bridge.c

   1 /*
   2  * (C) 2004 Linux Networx
   3  */
   4 #include <console/console.h>
   5 #include <device/device.h>
   6 #include <device/pci.h>
   7 #include <device/pci_ids.h>
   8 #include <device/pci_ops.h>
   9 #include <pc80/mc146818rtc.h>
  10
  11 static void amd8131_bus_read_resources(device_t dev)
  12 {
  13         return;
  14 }
  15
  16 static void amd8131_bus_set_resources(device_t dev)
  17 {
  18 #if 0
  19         pci_bus_read_resources(dev);
  20 #endif
  21         return;
  22 }
  23
  24 static void amd8131_bus_enable_resources(device_t dev)
  25 {
  26 #if 0
  27         pci_dev_set_resources(dev);
  28 #endif
  29         return;
  30 }
  31
  32 static void amd8131_bus_init(device_t dev)
  33 {
  34 #if 0
  35         pcix_init(dev);
  36 #endif
  37         return;
  38 }
  39
  40 static unsigned int amd8131_scan_bus(device_t bus, unsigned int max)
  41 {
  42 #if 0
  43         max = pcix_scan_bridge(bus, max);
  44 #endif
  45         return max;
  46 }
  47
  48 static void amd8131_enable(device_t dev)
  49 {
  50         uint32_t buses;
  51         uint16_t cr;
  52
  53         /* Clear all status bits and turn off memory, I/O and master enables. */
  54         pci_write_config16(dev, PCI_COMMAND, 0x0000);
  55         pci_write_config16(dev, PCI_STATUS, 0xffff);
  56
  57         /*
  58          * Read the existing primary/secondary/subordinate bus
  59          * number configuration.
  60          */
  61         buses = pci_read_config32(dev, PCI_PRIMARY_BUS);
  62
  63         /* Configure the bus numbers for this bridge: the configuration
  64          * transactions will not be propagated by the bridge if it is not
  65          * correctly configured.
  66          */
  67         buses &= 0xff000000;
  68         buses |= (((unsigned int) (dev->bus->secondary) << 0) |
  69                 ((unsigned int) (dev->bus->secondary) << 8) |
  70                 ((unsigned int) (dev->bus->secondary) << 16));
  71         pci_write_config32(dev, PCI_PRIMARY_BUS, buses);
  72 }
  73
  74 static struct device_operations pcix_ops  = {
  75         .read_resources   = amd8131_bus_read_resources,
  76         .set_resources    = amd8131_bus_set_resources,
  77         .enable_resources = amd8131_bus_enable_resources,
  78         .init             = amd8131_bus_init,
  79         .scan_bus         = 0,
  80         .enable           = amd8131_enable,
  81 };
  82
  83 static const struct pci_driver pcix_driver __pci_driver = {
  84         .ops    = &pcix_ops,
  85         .vendor = PCI_VENDOR_ID_AMD,
  86         .device = 0x7450,
  87 };
  88
  89
  90 static void ioapic_enable(device_t dev)
  91 {
  92         uint32_t value;
  93         value = pci_read_config32(dev, 0x44);
  94         if (dev->enabled) {
  95                 value |= ((1 << 1) | (1 << 0));
  96         } else {
  97                 value &= ~((1 << 1) | (1 << 0));
  98         }
  99         pci_write_config32(dev, 0x44, value);
 100 }
 101
 102 static struct device_operations ioapic_ops = {
 103         .read_resources   = pci_dev_read_resources,
 104         .set_resources    = pci_dev_set_resources,
 105         .enable_resources = pci_dev_enable_resources,
 106         .init     = 0,
 107         .scan_bus = 0,
 108         .enable   = ioapic_enable,
 109 };
 110
 111 static const struct pci_driver ioapic_driver __pci_driver = {
 112         .ops    = &ioapic_ops,
 113         .vendor = PCI_VENDOR_ID_AMD,
 114         .device = 0x7451,
 115
 116 };