src/southbridge/amd/amd8111/amd8111_nic.c

   1 /*
   2  * (C) 2003 Linux Networx
   3  */
   4 #include <console/console.h>
   5 #include <device/device.h>
   6 #include <device/pci.h>
   7 #include <device/pci_ids.h>
   8 #include <device/pci_ops.h>
   9 #include <arch/io.h>
  10 #include "amd8111.h"
  11
  12
  13 #define CMD3            0x54
  14
  15 typedef enum {
  16         VAL3                    = (1 << 31),   /* VAL bit for byte 3 */
  17         VAL2                    = (1 << 23),   /* VAL bit for byte 2 */
  18         VAL1                    = (1 << 15),   /* VAL bit for byte 1 */
  19         VAL0                    = (1 << 7),    /* VAL bit for byte 0 */
  20 }VAL_BITS;
  21
  22 typedef enum {
  23         /* VAL3 */
  24         ASF_INIT_DONE_ALIAS     = (1 << 29),
  25         /* VAL2 */
  26         JUMBO                   = (1 << 21),
  27         VSIZE                   = (1 << 20),
  28         VLONLY                  = (1 << 19),
  29         VL_TAG_DEL              = (1 << 18),
  30         /* VAL1 */
  31         EN_PMGR                 = (1 << 14),
  32         INTLEVEL                = (1 << 13),
  33         FORCE_FULL_DUPLEX       = (1 << 12),
  34         FORCE_LINK_STATUS       = (1 << 11),
  35         APEP                    = (1 << 10),
  36         MPPLBA                  = (1 << 9),
  37         /* VAL0 */
  38         RESET_PHY_PULSE         = (1 << 2),
  39         RESET_PHY               = (1 << 1),
  40         PHY_RST_POL             = (1 << 0),
  41 }CMD3_BITS;
  42
  43 static void nic_init(struct device *dev)
  44 {
  45         struct southbridge_amd_amd8111_config *conf;
  46         struct resource *resource;
  47         unsigned long mmio;
  48
  49         conf = dev->chip_info;
  50         resource = find_resource(dev, PCI_BASE_ADDRESS_0);
  51         mmio = resource->base;
  52
  53         /* Hard Reset PHY */
  54         printk_debug("Reseting PHY... ");
  55         if (conf->phy_lowreset) {
  56                 writel(VAL0 | PHY_RST_POL | RESET_PHY , (void *)(mmio + CMD3));
  57         } else {
  58                 writel(VAL0 | RESET_PHY, (void *)(mmio + CMD3));
  59         }
  60         mdelay(15);
  61         writel(RESET_PHY, (void *)(mmio + CMD3));
  62         printk_debug("Done\n");
  63 }
  64
  65 static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
  66 {
  67         pci_write_config32(dev, 0xc8,
  68                 ((device & 0xffff) << 16) | (vendor & 0xffff));
  69 }
  70
  71 static struct pci_operations lops_pci = {
  72         .set_subsystem = lpci_set_subsystem,
  73 };
  74
  75 static struct device_operations nic_ops  = {
  76         .read_resources   = pci_dev_read_resources,
  77         .set_resources    = pci_dev_set_resources,
  78         .enable_resources = pci_dev_enable_resources,
  79         .init             = nic_init,
  80         .scan_bus         = 0,
  81         .enable           = amd8111_enable,
  82         .ops_pci          = &lops_pci,
  83 };
  84
  85 static const struct pci_driver nic_driver __pci_driver = {
  86         .ops    = &nic_ops,
  87         .vendor = PCI_VENDOR_ID_AMD,
  88         .device = PCI_DEVICE_ID_AMD_8111_NIC,
  89 };