2 * (C) 2003 Linux Networx, SuSE Linux AG
3 * 2006.1 yhlu add dest apicid for IRQ0
5 #include <console/console.h>
6 #include <device/device.h>
7 #include <device/pci.h>
8 #include <device/pci_ids.h>
9 #include <device/pci_ops.h>
10 #include <pc80/mc146818rtc.h>
11 #include <pc80/isa-dma.h>
12 #include <cpu/x86/lapic.h>
20 unsigned int value_low, value_high;
23 static struct ioapicreg ioapicregvalues[] = {
24 #define ALL (0xff << 24)
26 #define DISABLED (1 << 16)
27 #define ENABLED (0 << 16)
28 #define TRIGGER_EDGE (0 << 15)
29 #define TRIGGER_LEVEL (1 << 15)
30 #define POLARITY_HIGH (0 << 13)
31 #define POLARITY_LOW (1 << 13)
32 #define PHYSICAL_DEST (0 << 11)
33 #define LOGICAL_DEST (1 << 11)
34 #define ExtINT (7 << 8)
38 /* IO-APIC virtual wire mode configuration */
39 /* mask, trigger, polarity, destination, delivery, vector */
40 { 0, ENABLED | TRIGGER_EDGE | POLARITY_HIGH | PHYSICAL_DEST | ExtINT, NONE},
50 { 10, DISABLED, NONE},
51 { 11, DISABLED, NONE},
52 { 12, DISABLED, NONE},
53 { 13, DISABLED, NONE},
54 { 14, DISABLED, NONE},
55 { 15, DISABLED, NONE},
56 { 16, DISABLED, NONE},
57 { 17, DISABLED, NONE},
58 { 18, DISABLED, NONE},
59 { 19, DISABLED, NONE},
60 { 20, DISABLED, NONE},
61 { 21, DISABLED, NONE},
62 { 22, DISABLED, NONE},
63 { 23, DISABLED, NONE},
64 /* Be careful and don't write past the end... */
67 static void setup_ioapic(void)
70 unsigned long value_low, value_high;
71 unsigned long ioapic_base = 0xfec00000;
72 volatile unsigned long *l;
73 struct ioapicreg *a = ioapicregvalues;
74 unsigned long bsp_apicid = lapicid();
76 l = (unsigned long *) ioapic_base;
78 ioapicregvalues[0].value_high = bsp_apicid<<(56-32);
79 printk_debug("amd8111: ioapic bsp_apicid = %02x\n", bsp_apicid);
81 for (i = 0; i < ARRAY_SIZE(ioapicregvalues);
83 l[0] = (a->reg * 2) + 0x10;
86 l[0] = (a->reg *2) + 0x11;
89 if ((i==0) && (value_low == 0xffffffff)) {
90 printk_warning("IO APIC not responding.\n");
93 printk_spew("for IRQ, reg 0x%08x value 0x%08x 0x%08x\n",
94 a->reg, a->value_low, a->value_high);
98 static void enable_hpet(struct device *dev)
100 unsigned long hpet_address;
102 pci_write_config32(dev,0xa0, 0xfed00001);
103 hpet_address = pci_read_config32(dev,0xa0)& 0xfffffffe;
104 printk_debug("enabling HPET @0x%x\n", hpet_address);
108 static void lpc_init(struct device *dev)
113 /* IO APIC initialization */
114 byte = pci_read_config8(dev, 0x4B);
116 pci_write_config8(dev, 0x4B, byte);
119 /* posted memory write enable */
120 byte = pci_read_config8(dev, 0x46);
121 pci_write_config8(dev, 0x46, byte | (1<<0));
123 /* Enable 5Mib Rom window */
124 byte = pci_read_config8(dev, 0x43);
126 pci_write_config8(dev, 0x43, byte);
128 /* Enable Port 92 fast reset */
129 byte = pci_read_config8(dev, 0x41);
131 pci_write_config8(dev, 0x41, byte);
133 /* Enable Error reporting */
134 /* Set up sync flood detected */
135 byte = pci_read_config8(dev, 0x47);
137 pci_write_config8(dev, 0x47, byte);
139 /* Set up NMI on errors */
140 byte = pci_read_config8(dev, 0x40);
141 byte |= (1 << 1); /* clear PW2LPC error */
142 byte |= (1 << 6); /* clear LPCERR */
143 pci_write_config8(dev, 0x40, byte);
144 nmi_option = NMI_OFF;
145 get_option(&nmi_option, "nmi");
147 byte |= (1 << 7); /* set NMI */
148 pci_write_config8(dev, 0x40, byte);
151 /* Initialize the real time clock */
154 /* Initialize isa dma */
157 /* Initialize the High Precision Event Timers */
161 static void amd8111_lpc_read_resources(device_t dev)
163 struct resource *res;
165 /* Get the normal pci resources of this device */
166 pci_dev_read_resources(dev);
168 /* Add an extra subtractive resource for both memory and I/O */
169 res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
170 res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
172 res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
173 res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
176 static void amd8111_lpc_enable_resources(device_t dev)
178 pci_dev_enable_resources(dev);
179 enable_childrens_resources(dev);
182 static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
184 pci_write_config32(dev, 0x70,
185 ((device & 0xffff) << 16) | (vendor & 0xffff));
188 static struct pci_operations lops_pci = {
189 .set_subsystem = lpci_set_subsystem,
192 static struct device_operations lpc_ops = {
193 .read_resources = amd8111_lpc_read_resources,
194 .set_resources = pci_dev_set_resources,
195 .enable_resources = amd8111_lpc_enable_resources,
197 .scan_bus = scan_static_bus,
198 .enable = amd8111_enable,
199 .ops_pci = &lops_pci,
202 static const struct pci_driver lpc_driver __pci_driver = {
204 .vendor = PCI_VENDOR_ID_AMD,
205 .device = PCI_DEVICE_ID_AMD_8111_ISA,