- Changes to the pci config routines moving them closer to the non romcc API
[coreboot.git] / src / southbridge / amd / amd8111 / amd8111_enable_rom.c
1
2 static void amd8111_enable_rom(void)
3 {
4         unsigned char byte;
5         device_t addr;
6
7         /* Enable 4MB rom access at 0xFFC00000 - 0xFFFFFFFF */
8         /* Locate the amd8111 */
9         addr = pci_locate_device(PCI_ID(0x1022, 0x7468), 0);
10         
11         /* Set the 4MB enable bit bit */
12         byte = pci_read_config8(addr, 0x43);
13         byte |= 0x80;
14         pci_write_config8(addr, 0x43, byte);
15 }