3 // Copyright (C) 2008 Kevin O'Connor <kevin@koconnor.net>
4 // Copyright (C) 2006 Fabrice Bellard
6 // This file may be distributed under the terms of the GNU LGPLv3 license.
8 #include "util.h" // dprintf
9 #include "config.h" // CONFIG_*
10 #include "cmos.h" // CMOS_BIOS_SMP_COUNT
13 #define APIC_ICR_LOW ((u8*)BUILD_APIC_ADDR + 0x300)
14 #define APIC_SVR ((u8*)BUILD_APIC_ADDR + 0x0F0)
15 #define APIC_LINT0 ((u8*)BUILD_APIC_ADDR + 0x350)
16 #define APIC_LINT1 ((u8*)BUILD_APIC_ADDR + 0x360)
18 #define APIC_ENABLED 0x0100
20 struct { u32 ecx, eax, edx; } smp_mtrr[16] VAR16VISIBLE;
21 u32 smp_mtrr_count VAR16VISIBLE;
24 wrmsr_smp(u32 index, u64 val)
27 if (smp_mtrr_count >= ARRAY_SIZE(smp_mtrr))
29 smp_mtrr[smp_mtrr_count].ecx = index;
30 smp_mtrr[smp_mtrr_count].eax = val;
31 smp_mtrr[smp_mtrr_count].edx = val >> 32;
35 u32 CountCPUs VAR16VISIBLE;
36 u32 MaxCountCPUs VAR16VISIBLE;
37 extern void smp_ap_boot_code(void);
39 " .global smp_ap_boot_code\n"
43 " movw $" __stringify(SEG_BIOS) ", %ax\n"
47 " movl $smp_mtrr, %esi\n"
48 " movl smp_mtrr_count, %ebx\n"
49 "1:testl %ebx, %ebx\n"
51 " movl 0(%esi), %ecx\n"
52 " movl 4(%esi), %eax\n"
53 " movl 8(%esi), %edx\n"
60 // Increment the cpu counter
61 " lock incl CountCPUs\n"
63 // Halt the processor.
68 // find and initialize the CPUs by launching a SIPI to them
73 u32 eax, ebx, ecx, cpuid_features;
74 cpuid(1, &eax, &ebx, &ecx, &cpuid_features);
75 if (eax < 1 || !(cpuid_features & CPUID_APIC)) {
76 // No apic - only the main cpu is present.
77 dprintf(1, "No apic - only the main cpu is present.\n");
84 writel(&CountCPUs, 1);
86 // Setup jump trampoline to counter code.
87 u64 old = *(u64*)BUILD_AP_BOOT_ADDR;
88 // ljmpw $SEG_BIOS, $(smp_ap_boot_code - BUILD_BIOS_ADDR)
89 u64 new = (0xea | ((u64)SEG_BIOS<<24)
90 | (((u32)smp_ap_boot_code - BUILD_BIOS_ADDR) << 8));
91 *(u64*)BUILD_AP_BOOT_ADDR = new;
94 u32 val = readl(APIC_SVR);
95 writel(APIC_SVR, val | APIC_ENABLED);
97 if (! CONFIG_COREBOOT) {
98 /* Set LINT0 as Ext_INT, level triggered */
99 writel(APIC_LINT0, 0x8700);
101 /* Set LINT1 as NMI, level triggered */
102 writel(APIC_LINT1, 0x8400);
107 writel(APIC_ICR_LOW, 0x000C4500);
108 u32 sipi_vector = BUILD_AP_BOOT_ADDR >> 12;
109 writel(APIC_ICR_LOW, 0x000C4600 | sipi_vector);
111 // Wait for other CPUs to process the SIPI.
112 if (CONFIG_COREBOOT) {
115 u8 cmos_smp_count = inb_cmos(CMOS_BIOS_SMP_COUNT);
116 while (cmos_smp_count + 1 != readl(&CountCPUs))
121 *(u64*)BUILD_AP_BOOT_ADDR = old;
123 MaxCountCPUs = qemu_cfg_get_max_cpus();
124 if (!MaxCountCPUs || MaxCountCPUs < CountCPUs)
125 MaxCountCPUs = CountCPUs;
127 dprintf(1, "Found %d cpu(s) max supported %d cpu(s)\n", readl(&CountCPUs),