1 // Support for enabling/disabling BIOS ram shadowing.
3 // Copyright (C) 2008,2009 Kevin O'Connor <kevin@koconnor.net>
4 // Copyright (C) 2006 Fabrice Bellard
6 // This file may be distributed under the terms of the GNU LGPLv3 license.
8 #include "util.h" // memcpy
9 #include "pci.h" // pci_config_writeb
10 #include "config.h" // CONFIG_*
11 #include "pci_ids.h" // PCI_VENDOR_ID_INTEL
13 // Test if 'addr' is in the range from 'start'..'start+size'
14 #define IN_RANGE(addr, start, size) ({ \
15 u32 __addr = (addr); \
16 u32 __start = (start); \
17 u32 __size = (size); \
18 (__addr - __start < __size); \
21 // On the emulators, the bios at 0xf0000 is also at 0xffff0000
22 #define BIOS_SRC_ADDR 0xffff0000
24 // Enable shadowing and copy bios.
26 __make_bios_writable(u16 bdf)
28 // Make ram from 0xc0000-0xf0000 writable
32 if (CONFIG_OPTIONROMS_DEPLOYED) {
33 int reg = pci_config_readb(bdf, 0x5a + i);
34 if ((reg & 0x11) != 0x11) {
35 // Need to copy optionroms to work around qemu implementation
36 void *mem = (void*)(BUILD_ROM_START + i * 32*1024);
37 memcpy((void*)BUILD_BIOS_TMP_ADDR, mem, 32*1024);
38 pci_config_writeb(bdf, 0x5a + i, 0x33);
39 memcpy(mem, (void*)BUILD_BIOS_TMP_ADDR, 32*1024);
42 pci_config_writeb(bdf, 0x5a + i, 0x33);
45 pci_config_writeb(bdf, 0x5a + i, 0x33);
49 memset((void*)BUILD_BIOS_TMP_ADDR, 0, 32*1024);
51 // Make ram from 0xf0000-0x100000 writable
52 int reg = pci_config_readb(bdf, 0x59);
53 pci_config_writeb(bdf, 0x59, 0x30);
55 // Ram already present.
59 memcpy((void*)BUILD_BIOS_ADDR, (void*)BIOS_SRC_ADDR, BUILD_BIOS_SIZE);
62 // Make the 0xc0000-0x100000 area read/writable.
69 dprintf(3, "enabling shadow ram\n");
71 // Locate chip controlling ram shadowing.
72 int bdf = pci_find_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441);
74 dprintf(1, "Unable to unlock ram - bridge not found\n");
78 int reg = pci_config_readb(bdf, 0x59);
80 // QEMU doesn't fully implement the piix shadow capabilities -
81 // if ram isn't backing the bios segment when shadowing is
82 // disabled, the code itself wont be in memory. So, run the
83 // code from the high-memory flash location.
84 u32 pos = (u32)__make_bios_writable - BUILD_BIOS_ADDR + BIOS_SRC_ADDR;
85 void (*func)(u16 bdf) = (void*)pos;
89 // Ram already present - just enable writes
90 __make_bios_writable(bdf);
93 // Make the BIOS code segment area (0xf0000) read-only.
100 dprintf(3, "locking shadow ram\n");
102 int bdf = pci_find_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441);
104 dprintf(1, "Unable to lock ram - bridge not found\n");
108 // Flush any pending writes before locking memory.
111 // Write protect roms from 0xc0000-0xf0000
113 for (i=0; i<6; i++) {
114 u32 mem = BUILD_ROM_START + i * 32*1024;
115 if (RomEnd <= mem + 16*1024) {
117 pci_config_writeb(bdf, 0x5a + i, 0x31);
120 pci_config_writeb(bdf, 0x5a + i, 0x11);
123 // Write protect 0xf0000-0x100000
124 pci_config_writeb(bdf, 0x59, 0x10);