1 /////////////////////////////////////////////////////////////////////////
3 // 32 bit Bochs BIOS init code
4 // Copyright (C) 2006 Fabrice Bellard
6 // This library is free software; you can redistribute it and/or
7 // modify it under the terms of the GNU Lesser General Public
8 // License as published by the Free Software Foundation; either
9 // version 2 of the License, or (at your option) any later version.
11 // This library is distributed in the hope that it will be useful,
12 // but WITHOUT ANY WARRANTY; without even the implied warranty of
13 // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 // Lesser General Public License for more details.
16 // You should have received a copy of the GNU Lesser General Public
17 // License along with this library; if not, write to the Free Software
18 // Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
20 #include "util.h" // BX_INFO
21 #include "pci.h" // PCIDevice
22 #include "types.h" // u32
23 #include "config.h" // CONFIG_*
25 // Memory addresses used by this code. (Note global variables (bss)
27 #define CPU_COUNT_ADDR 0xf000
28 #define AP_BOOT_ADDR 0x10000
29 #define BIOS_TMP_STORAGE 0x30000 /* 64 KB used to copy the BIOS to shadow RAM */
31 #define PM_IO_BASE 0xb000
32 #define SMB_IO_BASE 0xb100
34 #define cpuid(index, eax, ebx, ecx, edx) \
35 asm volatile ("cpuid" \
36 : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx) \
39 #define wbinvd() asm volatile("wbinvd")
41 #define CPUID_APIC (1 << 9)
43 #define APIC_BASE ((u8 *)0xfee00000)
44 #define APIC_ICR_LOW 0x300
45 #define APIC_SVR 0x0F0
47 #define APIC_LVT3 0x370
49 #define APIC_ENABLED 0x0100
51 #define MPTABLE_MAX_SIZE 0x00002000
52 #define SMI_CMD_IO_ADDR 0xb2
54 static inline void writel(void *addr, u32 val)
56 *(volatile u32 *)addr = val;
59 static inline void writew(void *addr, u16 val)
61 *(volatile u16 *)addr = val;
64 static inline void writeb(void *addr, u8 val)
66 *(volatile u8 *)addr = val;
69 static inline u32 readl(const void *addr)
71 return *(volatile const u32 *)addr;
74 static inline u16 readw(const void *addr)
76 return *(volatile const u16 *)addr;
79 static inline u8 readb(const void *addr)
81 return *(volatile const u8 *)addr;
87 u32 cpuid_ext_features;
89 #if (CONFIG_USE_EBDA_TABLES == 1)
90 unsigned long ebda_cur_addr;
93 u32 pm_io_base, smb_io_base;
95 unsigned long bios_table_cur_addr;
96 unsigned long bios_table_end_addr;
100 #if (CONFIG_QEMU == 1)
101 u32 eax, ebx, ecx, edx;
103 // check if backdoor port exists
104 asm volatile ("outl %%eax, %%dx"
105 : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx)
106 : "a" (0x564d5868), "c" (0xa), "d" (0x5658));
107 if (ebx == 0x564d5868) {
108 u32 *uuid_ptr = (u32 *)bios_uuid;
110 asm volatile ("outl %%eax, %%dx"
111 : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx)
112 : "a" (0x564d5868), "c" (0x13), "d" (0x5658));
121 memset(bios_uuid, 0, 16);
127 u32 eax, ebx, ecx, edx;
128 cpuid(1, eax, ebx, ecx, edx);
129 cpuid_signature = eax;
130 cpuid_features = edx;
131 cpuid_ext_features = ecx;
134 /****************************************************/
137 extern u8 smp_ap_boot_code_start;
138 extern u8 smp_ap_boot_code_end;
140 /* find the number of CPUs by launching a SIPI to them */
143 u32 val, sipi_vector;
146 if (cpuid_features & CPUID_APIC) {
148 /* enable local APIC */
149 val = readl(APIC_BASE + APIC_SVR);
151 writel(APIC_BASE + APIC_SVR, val);
153 writew((void *)CPU_COUNT_ADDR, 1);
154 /* copy AP boot code */
155 memcpy((void *)AP_BOOT_ADDR, &smp_ap_boot_code_start,
156 &smp_ap_boot_code_end - &smp_ap_boot_code_start);
159 writel(APIC_BASE + APIC_ICR_LOW, 0x000C4500);
160 sipi_vector = AP_BOOT_ADDR >> 12;
161 writel(APIC_BASE + APIC_ICR_LOW, 0x000C4600 | sipi_vector);
165 smp_cpus = readw((void *)CPU_COUNT_ADDR);
167 BX_INFO("Found %d cpu(s)\n", smp_cpus);
170 /****************************************************/
173 #define PCI_ADDRESS_SPACE_MEM 0x00
174 #define PCI_ADDRESS_SPACE_IO 0x01
175 #define PCI_ADDRESS_SPACE_MEM_PREFETCH 0x08
177 #define PCI_ROM_SLOT 6
178 #define PCI_NUM_REGIONS 7
180 #define PCI_DEVICES_MAX 64
182 #define PCI_VENDOR_ID 0x00 /* 16 bits */
183 #define PCI_DEVICE_ID 0x02 /* 16 bits */
184 #define PCI_COMMAND 0x04 /* 16 bits */
185 #define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
186 #define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
187 #define PCI_CLASS_DEVICE 0x0a /* Device class */
188 #define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
189 #define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
190 #define PCI_MIN_GNT 0x3e /* 8 bits */
191 #define PCI_MAX_LAT 0x3f /* 8 bits */
193 static u32 pci_bios_io_addr;
194 static u32 pci_bios_mem_addr;
195 static u32 pci_bios_bigmem_addr;
196 /* host irqs corresponding to PCI irqs A-D */
197 static u8 pci_irqs[4] = { 11, 9, 11, 9 };
198 static PCIDevice i440_pcidev;
200 static void pci_set_io_region_addr(PCIDevice *d, int region_num, u32 addr)
205 if ( region_num == PCI_ROM_SLOT ) {
208 ofs = 0x10 + region_num * 4;
211 old_addr = pci_config_readl(d, ofs);
213 pci_config_writel(d, ofs, addr);
214 BX_INFO("region %d: 0x%08x\n", region_num, addr);
216 /* enable memory mappings */
217 cmd = pci_config_readw(d, PCI_COMMAND);
218 if ( region_num == PCI_ROM_SLOT )
220 else if (old_addr & PCI_ADDRESS_SPACE_IO)
224 pci_config_writew(d, PCI_COMMAND, cmd);
227 /* return the global irq number corresponding to a given device irq
228 pin. We could also use the bus number to have a more precise
230 static int pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num)
233 slot_addend = (pci_dev->devfn >> 3) - 1;
234 return (irq_num + slot_addend) & 3;
238 copy_bios(PCIDevice *d, int v)
240 pci_config_writeb(d, 0x59, v);
241 memcpy((void *)0x000f0000, (void *)BIOS_TMP_STORAGE, 0x10000);
244 // Test if 'addr' is in the range from 'start'..'start+size'
245 #define IN_RANGE(addr, start, size) ({ \
246 u32 __addr = (addr); \
247 u32 __start = (start); \
248 u32 __size = (size); \
249 (__addr - __start < __size); \
252 static void bios_shadow_init(PCIDevice *d)
254 bios_table_cur_addr = 0xf0000 | OFFSET_freespace2_start;
255 bios_table_end_addr = 0xf0000 | OFFSET_freespace2_end;
256 BX_INFO("bios_table_addr: 0x%08lx end=0x%08lx\n",
257 bios_table_cur_addr, bios_table_end_addr);
259 /* remap the BIOS to shadow RAM an keep it read/write while we
260 are writing tables */
261 int v = pci_config_readb(d, 0x59);
263 pci_config_writeb(d, 0x59, v);
264 memcpy((void *)BIOS_TMP_STORAGE, (void *)0x000f0000, 0x10000);
267 if (IN_RANGE((u32)copy_bios, 0xf0000, 0x10000)) {
268 // Current code is in shadowed area. Perform the copy from
269 // the code that is in the temporary location.
270 u32 pos = (u32)copy_bios - 0xf0000 + BIOS_TMP_STORAGE;
271 void (*func)(PCIDevice *, int) = (void*)pos;
277 // Clear the area just copied.
278 memset((void *)BIOS_TMP_STORAGE, 0, 0x10000);
283 static void bios_lock_shadow_ram(void)
285 PCIDevice *d = &i440_pcidev;
289 v = pci_config_readb(d, 0x59);
290 v = (v & 0x0f) | (0x10);
291 pci_config_writeb(d, 0x59, v);
294 static void pci_bios_init_bridges(PCIDevice *d)
296 u16 vendor_id, device_id;
298 vendor_id = pci_config_readw(d, PCI_VENDOR_ID);
299 device_id = pci_config_readw(d, PCI_DEVICE_ID);
301 if (vendor_id == 0x8086 && device_id == 0x7000) {
309 for(i = 0; i < 4; i++) {
311 /* set to trigger level */
312 elcr[irq >> 3] |= (1 << (irq & 7));
313 /* activate irq remapping in PIIX */
314 pci_config_writeb(d, 0x60 + i, irq);
316 outb(elcr[0], 0x4d0);
317 outb(elcr[1], 0x4d1);
318 BX_INFO("PIIX3 init: elcr=%02x %02x\n",
320 } else if (vendor_id == 0x8086 && device_id == 0x1237) {
321 /* i440 PCI bridge */
327 ".globl smp_ap_boot_code_start\n"
328 ".globl smp_ap_boot_code_end\n"
329 ".global smm_relocation_start\n"
330 ".global smm_relocation_end\n"
331 ".global smm_code_start\n"
332 ".global smm_code_end\n"
335 "smp_ap_boot_code_start:\n"
338 " incw " __stringify(CPU_COUNT_ADDR) "\n"
342 "smp_ap_boot_code_end:\n"
344 /* code to relocate SMBASE to 0xa0000 */
345 "smm_relocation_start:\n"
346 " mov $0x38000 + 0x7efc, %ebx\n"
347 " addr32 mov (%ebx), %al\n" /* revision ID to see if x86_64 or x86 */
350 " mov $0x38000 + 0x7ef8, %ebx\n"
353 " mov $0x38000 + 0x7f00, %ebx\n"
355 " movl $0xa0000, %eax\n"
356 " addr32 movl %eax, (%ebx)\n"
357 /* indicate to the BIOS that the SMM code was executed */
362 "smm_relocation_end:\n"
364 /* minimal SMM code to enable or disable ACPI */
372 " mov $" __stringify(PM_IO_BASE) " + 0x04, %dx\n" /* PMCNTRL */
384 " mov $" __stringify(PM_IO_BASE) " + 0x04, %dx\n" /* PMCNTRL */
395 extern u8 smm_relocation_start, smm_relocation_end;
396 extern u8 smm_code_start, smm_code_end;
398 #if (CONFIG_USE_SMM == 1)
399 static void smm_init(PCIDevice *d)
403 /* check if SMM init is already done */
404 value = pci_config_readl(d, 0x58);
405 if ((value & (1 << 25)) == 0) {
407 /* copy the SMM relocation code */
408 memcpy((void *)0x38000, &smm_relocation_start,
409 &smm_relocation_end - &smm_relocation_start);
411 /* enable SMI generation when writing to the APMC register */
412 pci_config_writel(d, 0x58, value | (1 << 25));
414 /* init APM status port */
417 /* raise an SMI interrupt */
420 /* wait until SMM code executed */
421 while (inb(0xb3) != 0x00)
424 /* enable the SMM memory window */
425 pci_config_writeb(&i440_pcidev, 0x72, 0x02 | 0x48);
427 /* copy the SMM code */
428 memcpy((void *)0xa8000, &smm_code_start,
429 &smm_code_end - &smm_code_start);
432 /* close the SMM memory window and enable normal SMM */
433 pci_config_writeb(&i440_pcidev, 0x72, 0x02 | 0x08);
438 static void pci_bios_init_device(PCIDevice *d)
442 int i, pin, pic_irq, vendor_id, device_id;
444 class = pci_config_readw(d, PCI_CLASS_DEVICE);
445 vendor_id = pci_config_readw(d, PCI_VENDOR_ID);
446 device_id = pci_config_readw(d, PCI_DEVICE_ID);
447 BX_INFO("PCI: bus=%d devfn=0x%02x: vendor_id=0x%04x device_id=0x%04x\n",
448 d->bus, d->devfn, vendor_id, device_id);
451 if (vendor_id == 0x8086 && device_id == 0x7010) {
453 pci_config_writew(d, 0x40, 0x8000); // enable IDE0
454 pci_config_writew(d, 0x42, 0x8000); // enable IDE1
457 /* IDE: we map it as in ISA mode */
458 pci_set_io_region_addr(d, 0, 0x1f0);
459 pci_set_io_region_addr(d, 1, 0x3f4);
460 pci_set_io_region_addr(d, 2, 0x170);
461 pci_set_io_region_addr(d, 3, 0x374);
465 if (vendor_id != 0x1234)
467 /* VGA: map frame buffer to default Bochs VBE address */
468 pci_set_io_region_addr(d, 0, 0xE0000000);
472 if (vendor_id == 0x1014) {
474 if (device_id == 0x0046 || device_id == 0xFFFF) {
476 pci_set_io_region_addr(d, 0, 0x80800000 + 0x00040000);
481 if (vendor_id == 0x0106b &&
482 (device_id == 0x0017 || device_id == 0x0022)) {
484 pci_set_io_region_addr(d, 0, 0x80800000);
489 /* default memory mappings */
490 for(i = 0; i < PCI_NUM_REGIONS; i++) {
494 if (i == PCI_ROM_SLOT)
498 pci_config_writel(d, ofs, 0xffffffff);
499 val = pci_config_readl(d, ofs);
501 size = (~(val & ~0xf)) + 1;
502 if (val & PCI_ADDRESS_SPACE_IO)
503 paddr = &pci_bios_io_addr;
504 else if (size >= 0x04000000)
505 paddr = &pci_bios_bigmem_addr;
507 paddr = &pci_bios_mem_addr;
508 *paddr = (*paddr + size - 1) & ~(size - 1);
509 pci_set_io_region_addr(d, i, *paddr);
516 /* map the interrupt */
517 pin = pci_config_readb(d, PCI_INTERRUPT_PIN);
519 pin = pci_slot_get_pirq(d, pin - 1);
520 pic_irq = pci_irqs[pin];
521 pci_config_writeb(d, PCI_INTERRUPT_LINE, pic_irq);
524 if (vendor_id == 0x8086 && device_id == 0x7113) {
525 /* PIIX4 Power Management device (for ACPI) */
526 pm_io_base = PM_IO_BASE;
527 pci_config_writel(d, 0x40, pm_io_base | 1);
528 pci_config_writeb(d, 0x80, 0x01); /* enable PM io space */
529 smb_io_base = SMB_IO_BASE;
530 pci_config_writel(d, 0x90, smb_io_base | 1);
531 pci_config_writeb(d, 0xd2, 0x09); /* enable SMBus io space */
532 pm_sci_int = pci_config_readb(d, PCI_INTERRUPT_LINE);
533 #if (CONFIG_USE_SMM == 1)
540 void pci_for_each_device(void (*init_func)(PCIDevice *d))
542 PCIDevice d1, *d = &d1;
544 u16 vendor_id, device_id;
546 for(bus = 0; bus < 1; bus++) {
547 for(devfn = 0; devfn < 256; devfn++) {
550 vendor_id = pci_config_readw(d, PCI_VENDOR_ID);
551 device_id = pci_config_readw(d, PCI_DEVICE_ID);
552 if (vendor_id != 0xffff || device_id != 0xffff) {
559 void pci_bios_init(void)
561 pci_bios_io_addr = 0xc000;
562 pci_bios_mem_addr = 0xf0000000;
563 pci_bios_bigmem_addr = GET_EBDA(ram_size);
564 if (pci_bios_bigmem_addr < 0x90000000)
565 pci_bios_bigmem_addr = 0x90000000;
567 pci_for_each_device(pci_bios_init_bridges);
569 pci_for_each_device(pci_bios_init_device);
572 /****************************************************/
573 /* Multi Processor table init */
575 static void putb(u8 **pp, int val)
583 static void putstr(u8 **pp, const char *str)
592 static void putle16(u8 **pp, int val)
601 static void putle32(u8 **pp, int val)
612 static unsigned long align(unsigned long addr, unsigned long v)
614 return (addr + v - 1) & ~(v - 1);
617 static void mptable_init(void)
619 u8 *mp_config_table, *q, *float_pointer_struct;
620 int ioapic_id, i, len;
621 int mp_config_table_size;
623 #if (CONFIG_QEMU == 1)
628 #if (CONFIG_USE_EBDA_TABLES == 1)
629 mp_config_table = (u8 *)(GET_EBDA(ram_size) - CONFIG_ACPI_DATA_SIZE
632 bios_table_cur_addr = align(bios_table_cur_addr, 16);
633 mp_config_table = (u8 *)bios_table_cur_addr;
636 putstr(&q, "PCMP"); /* "PCMP signature */
637 putle16(&q, 0); /* table length (patched later) */
638 putb(&q, 4); /* spec rev */
639 putb(&q, 0); /* checksum (patched later) */
640 #if (CONFIG_QEMU == 1)
641 putstr(&q, "QEMUCPU "); /* OEM id */
643 putstr(&q, "BOCHSCPU");
645 putstr(&q, "0.1 "); /* vendor id */
646 putle32(&q, 0); /* OEM table ptr */
647 putle16(&q, 0); /* OEM table size */
648 putle16(&q, smp_cpus + 18); /* entry count */
649 putle32(&q, 0xfee00000); /* local APIC addr */
650 putle16(&q, 0); /* ext table length */
651 putb(&q, 0); /* ext table checksum */
652 putb(&q, 0); /* reserved */
654 for(i = 0; i < smp_cpus; i++) {
655 putb(&q, 0); /* entry type = processor */
656 putb(&q, i); /* APIC id */
657 putb(&q, 0x11); /* local APIC version number */
659 putb(&q, 3); /* cpu flags: enabled, bootstrap cpu */
661 putb(&q, 1); /* cpu flags: enabled */
662 putb(&q, 0); /* cpu signature */
666 putle16(&q, 0x201); /* feature flags */
669 putle16(&q, 0); /* reserved */
676 putb(&q, 1); /* entry type = bus */
677 putb(&q, 0); /* bus ID */
681 ioapic_id = smp_cpus;
682 putb(&q, 2); /* entry type = I/O APIC */
683 putb(&q, ioapic_id); /* apic ID */
684 putb(&q, 0x11); /* I/O APIC version number */
685 putb(&q, 1); /* enable */
686 putle32(&q, 0xfec00000); /* I/O APIC addr */
689 for(i = 0; i < 16; i++) {
690 putb(&q, 3); /* entry type = I/O interrupt */
691 putb(&q, 0); /* interrupt type = vectored interrupt */
692 putb(&q, 0); /* flags: po=0, el=0 */
694 putb(&q, 0); /* source bus ID = ISA */
695 putb(&q, i); /* source bus IRQ */
696 putb(&q, ioapic_id); /* dest I/O APIC ID */
697 putb(&q, i); /* dest I/O APIC interrupt in */
700 len = q - mp_config_table;
701 mp_config_table[4] = len;
702 mp_config_table[5] = len >> 8;
704 mp_config_table[7] = -checksum(mp_config_table, q - mp_config_table);
706 mp_config_table_size = q - mp_config_table;
708 #if (CONFIG_USE_EBDA_TABLES != 1)
709 bios_table_cur_addr += mp_config_table_size;
712 /* floating pointer structure */
713 #if (CONFIG_USE_EBDA_TABLES == 1)
714 ebda_cur_addr = align(ebda_cur_addr, 16);
715 float_pointer_struct = (u8 *)ebda_cur_addr;
717 bios_table_cur_addr = align(bios_table_cur_addr, 16);
718 float_pointer_struct = (u8 *)bios_table_cur_addr;
720 q = float_pointer_struct;
722 /* pointer to MP config table */
723 putle32(&q, (unsigned long)mp_config_table);
725 putb(&q, 1); /* length in 16 byte units */
726 putb(&q, 4); /* MP spec revision */
727 putb(&q, 0); /* checksum (patched later) */
728 putb(&q, 0); /* MP feature byte 1 */
734 float_pointer_struct[10] = -checksum(float_pointer_struct
735 , q - float_pointer_struct);
736 #if (CONFIG_USE_EBDA_TABLES == 1)
737 ebda_cur_addr += (q - float_pointer_struct);
739 bios_table_cur_addr += (q - float_pointer_struct);
741 BX_INFO("MP table addr=0x%08lx MPC table addr=0x%08lx size=0x%x\n",
742 (unsigned long)float_pointer_struct,
743 (unsigned long)mp_config_table,
744 mp_config_table_size);
747 /****************************************************/
748 /* ACPI tables init */
750 /* Table structure from Linux kernel (the ACPI tables are under the
753 #define ACPI_TABLE_HEADER_DEF /* ACPI common table header */ \
754 u8 signature [4]; /* ACPI signature (4 ASCII characters) */\
755 u32 length; /* Length of table, in bytes, including header */\
756 u8 revision; /* ACPI Specification minor version # */\
757 u8 checksum; /* To make sum of entire table == 0 */\
758 u8 oem_id [6]; /* OEM identification */\
759 u8 oem_table_id [8]; /* OEM table identification */\
760 u32 oem_revision; /* OEM revision number */\
761 u8 asl_compiler_id [4]; /* ASL compiler vendor ID */\
762 u32 asl_compiler_revision; /* ASL compiler revision number */
765 struct acpi_table_header /* ACPI common table header */
767 ACPI_TABLE_HEADER_DEF
770 struct rsdp_descriptor /* Root System Descriptor Pointer */
772 u8 signature [8]; /* ACPI signature, contains "RSD PTR " */
773 u8 checksum; /* To make sum of struct == 0 */
774 u8 oem_id [6]; /* OEM identification */
775 u8 revision; /* Must be 0 for 1.0, 2 for 2.0 */
776 u32 rsdt_physical_address; /* 32-bit physical address of RSDT */
777 u32 length; /* XSDT Length in bytes including hdr */
778 u64 xsdt_physical_address; /* 64-bit physical address of XSDT */
779 u8 extended_checksum; /* Checksum of entire table */
780 u8 reserved [3]; /* Reserved field must be 0 */
784 * ACPI 1.0 Root System Description Table (RSDT)
786 struct rsdt_descriptor_rev1
788 ACPI_TABLE_HEADER_DEF /* ACPI common table header */
789 u32 table_offset_entry [3]; /* Array of pointers to other */
794 * ACPI 1.0 Firmware ACPI Control Structure (FACS)
796 struct facs_descriptor_rev1
798 u8 signature[4]; /* ACPI Signature */
799 u32 length; /* Length of structure, in bytes */
800 u32 hardware_signature; /* Hardware configuration signature */
801 u32 firmware_waking_vector; /* ACPI OS waking vector */
802 u32 global_lock; /* Global Lock */
803 u32 S4bios_f : 1; /* Indicates if S4BIOS support is present */
804 u32 reserved1 : 31; /* Must be 0 */
805 u8 resverved3 [40]; /* Reserved - must be zero */
810 * ACPI 1.0 Fixed ACPI Description Table (FADT)
812 struct fadt_descriptor_rev1
814 ACPI_TABLE_HEADER_DEF /* ACPI common table header */
815 u32 firmware_ctrl; /* Physical address of FACS */
816 u32 dsdt; /* Physical address of DSDT */
817 u8 model; /* System Interrupt Model */
818 u8 reserved1; /* Reserved */
819 u16 sci_int; /* System vector of SCI interrupt */
820 u32 smi_cmd; /* Port address of SMI command port */
821 u8 acpi_enable; /* Value to write to smi_cmd to enable ACPI */
822 u8 acpi_disable; /* Value to write to smi_cmd to disable ACPI */
823 u8 S4bios_req; /* Value to write to SMI CMD to enter S4BIOS state */
824 u8 reserved2; /* Reserved - must be zero */
825 u32 pm1a_evt_blk; /* Port address of Power Mgt 1a acpi_event Reg Blk */
826 u32 pm1b_evt_blk; /* Port address of Power Mgt 1b acpi_event Reg Blk */
827 u32 pm1a_cnt_blk; /* Port address of Power Mgt 1a Control Reg Blk */
828 u32 pm1b_cnt_blk; /* Port address of Power Mgt 1b Control Reg Blk */
829 u32 pm2_cnt_blk; /* Port address of Power Mgt 2 Control Reg Blk */
830 u32 pm_tmr_blk; /* Port address of Power Mgt Timer Ctrl Reg Blk */
831 u32 gpe0_blk; /* Port addr of General Purpose acpi_event 0 Reg Blk */
832 u32 gpe1_blk; /* Port addr of General Purpose acpi_event 1 Reg Blk */
833 u8 pm1_evt_len; /* Byte length of ports at pm1_x_evt_blk */
834 u8 pm1_cnt_len; /* Byte length of ports at pm1_x_cnt_blk */
835 u8 pm2_cnt_len; /* Byte Length of ports at pm2_cnt_blk */
836 u8 pm_tmr_len; /* Byte Length of ports at pm_tm_blk */
837 u8 gpe0_blk_len; /* Byte Length of ports at gpe0_blk */
838 u8 gpe1_blk_len; /* Byte Length of ports at gpe1_blk */
839 u8 gpe1_base; /* Offset in gpe model where gpe1 events start */
840 u8 reserved3; /* Reserved */
841 u16 plvl2_lat; /* Worst case HW latency to enter/exit C2 state */
842 u16 plvl3_lat; /* Worst case HW latency to enter/exit C3 state */
843 u16 flush_size; /* Size of area read to flush caches */
844 u16 flush_stride; /* Stride used in flushing caches */
845 u8 duty_offset; /* Bit location of duty cycle field in p_cnt reg */
846 u8 duty_width; /* Bit width of duty cycle field in p_cnt reg */
847 u8 day_alrm; /* Index to day-of-month alarm in RTC CMOS RAM */
848 u8 mon_alrm; /* Index to month-of-year alarm in RTC CMOS RAM */
849 u8 century; /* Index to century in RTC CMOS RAM */
850 u8 reserved4; /* Reserved */
851 u8 reserved4a; /* Reserved */
852 u8 reserved4b; /* Reserved */
854 u32 wb_invd : 1; /* The wbinvd instruction works properly */
855 u32 wb_invd_flush : 1; /* The wbinvd flushes but does not invalidate */
856 u32 proc_c1 : 1; /* All processors support C1 state */
857 u32 plvl2_up : 1; /* C2 state works on MP system */
858 u32 pwr_button : 1; /* Power button is handled as a generic feature */
859 u32 sleep_button : 1; /* Sleep button is handled as a generic feature, or not present */
860 u32 fixed_rTC : 1; /* RTC wakeup stat not in fixed register space */
861 u32 rtcs4 : 1; /* RTC wakeup stat not possible from S4 */
862 u32 tmr_val_ext : 1; /* The tmr_val width is 32 bits (0 = 24 bits) */
863 u32 reserved5 : 23; /* Reserved - must be zero */
870 * MADT values and structures
873 /* Values for MADT PCATCompat */
876 #define MULTIPLE_APIC 1
881 struct multiple_apic_table
883 ACPI_TABLE_HEADER_DEF /* ACPI common table header */
884 u32 local_apic_address; /* Physical address of local APIC */
886 u32 PCATcompat : 1; /* A one indicates system also has dual 8259s */
894 /* Values for Type in APIC_HEADER_DEF */
896 #define APIC_PROCESSOR 0
898 #define APIC_XRUPT_OVERRIDE 2
900 #define APIC_LOCAL_NMI 4
901 #define APIC_ADDRESS_OVERRIDE 5
902 #define APIC_IO_SAPIC 6
903 #define APIC_LOCAL_SAPIC 7
904 #define APIC_XRUPT_SOURCE 8
905 #define APIC_RESERVED 9 /* 9 and greater are reserved */
908 * MADT sub-structures (Follow MULTIPLE_APIC_DESCRIPTION_TABLE)
910 #define APIC_HEADER_DEF /* Common APIC sub-structure header */\
914 /* Sub-structures for MADT */
916 struct madt_processor_apic
919 u8 processor_id; /* ACPI processor id */
920 u8 local_apic_id; /* Processor's local APIC id */
922 u32 processor_enabled: 1; /* Processor is usable if set */
923 u32 reserved2 : 31; /* Reserved, must be zero */
932 u8 io_apic_id; /* I/O APIC ID */
933 u8 reserved; /* Reserved - must be zero */
934 u32 address; /* APIC physical address */
935 u32 interrupt; /* Global system interrupt where INTI
939 #include "acpi-dsdt.hex"
941 static inline u16 cpu_to_le16(u16 x)
946 static inline u32 cpu_to_le32(u32 x)
951 static void acpi_build_table_header(struct acpi_table_header *h,
952 char *sig, int len, u8 rev)
954 memcpy(h->signature, sig, 4);
955 h->length = cpu_to_le32(len);
957 #if (CONFIG_QEMU == 1)
958 memcpy(h->oem_id, "QEMU ", 6);
959 memcpy(h->oem_table_id, "QEMU", 4);
961 memcpy(h->oem_id, "BOCHS ", 6);
962 memcpy(h->oem_table_id, "BXPC", 4);
964 memcpy(h->oem_table_id + 4, sig, 4);
965 h->oem_revision = cpu_to_le32(1);
966 #if (CONFIG_QEMU == 1)
967 memcpy(h->asl_compiler_id, "QEMU", 4);
969 memcpy(h->asl_compiler_id, "BXPC", 4);
971 h->asl_compiler_revision = cpu_to_le32(1);
972 h->checksum = -checksum((void *)h, len);
975 int acpi_build_processor_ssdt(u8 *ssdt)
979 int acpi_cpus = smp_cpus > 0xff ? 0xff : smp_cpus;
981 ssdt_ptr[9] = 0; // checksum;
982 ssdt_ptr += sizeof(struct acpi_table_header);
984 // caluculate the length of processor block and scope block excluding PkgLength
985 length = 0x0d * acpi_cpus + 4;
987 // build processor scope header
988 *(ssdt_ptr++) = 0x10; // ScopeOp
989 if (length <= 0x3e) {
990 *(ssdt_ptr++) = length + 1;
992 *(ssdt_ptr++) = 0x7F;
993 *(ssdt_ptr++) = (length + 2) >> 6;
995 *(ssdt_ptr++) = '_'; // Name
1000 // build object for each processor
1001 for(i=0;i<acpi_cpus;i++) {
1002 *(ssdt_ptr++) = 0x5B; // ProcessorOp
1003 *(ssdt_ptr++) = 0x83;
1004 *(ssdt_ptr++) = 0x0B; // Length
1005 *(ssdt_ptr++) = 'C'; // Name (CPUxx)
1006 *(ssdt_ptr++) = 'P';
1007 if ((i & 0xf0) != 0)
1008 *(ssdt_ptr++) = (i >> 4) < 0xa ? (i >> 4) + '0' : (i >> 4) + 'A' - 0xa;
1010 *(ssdt_ptr++) = 'U';
1011 *(ssdt_ptr++) = (i & 0xf) < 0xa ? (i & 0xf) + '0' : (i & 0xf) + 'A' - 0xa;
1013 *(ssdt_ptr++) = 0x10; // Processor block address
1014 *(ssdt_ptr++) = 0xb0;
1017 *(ssdt_ptr++) = 6; // Processor block length
1020 acpi_build_table_header((struct acpi_table_header *)ssdt,
1021 "SSDT", ssdt_ptr - ssdt, 1);
1023 return ssdt_ptr - ssdt;
1026 /* base_addr must be a multiple of 4KB */
1027 void acpi_bios_init(void)
1029 struct rsdp_descriptor *rsdp;
1030 struct rsdt_descriptor_rev1 *rsdt;
1031 struct fadt_descriptor_rev1 *fadt;
1032 struct facs_descriptor_rev1 *facs;
1033 struct multiple_apic_table *madt;
1035 u32 base_addr, rsdt_addr, fadt_addr, addr, facs_addr, dsdt_addr, ssdt_addr;
1036 u32 acpi_tables_size, madt_addr, madt_size;
1039 /* reserve memory space for tables */
1040 #if (CONFIG_USE_EBDA_TABLES == 1)
1041 ebda_cur_addr = align(ebda_cur_addr, 16);
1042 rsdp = (void *)(ebda_cur_addr);
1043 ebda_cur_addr += sizeof(*rsdp);
1045 bios_table_cur_addr = align(bios_table_cur_addr, 16);
1046 rsdp = (void *)(bios_table_cur_addr);
1047 bios_table_cur_addr += sizeof(*rsdp);
1050 addr = base_addr = GET_EBDA(ram_size) - CONFIG_ACPI_DATA_SIZE;
1052 rsdt = (void *)(addr);
1053 addr += sizeof(*rsdt);
1056 fadt = (void *)(addr);
1057 addr += sizeof(*fadt);
1059 /* XXX: FACS should be in RAM */
1060 addr = (addr + 63) & ~63; /* 64 byte alignment for FACS */
1062 facs = (void *)(addr);
1063 addr += sizeof(*facs);
1066 dsdt = (void *)(addr);
1067 addr += sizeof(AmlCode);
1070 ssdt = (void *)(addr);
1071 addr += acpi_build_processor_ssdt(ssdt);
1073 addr = (addr + 7) & ~7;
1075 madt_size = sizeof(*madt) +
1076 sizeof(struct madt_processor_apic) * smp_cpus +
1077 sizeof(struct madt_io_apic);
1078 madt = (void *)(addr);
1081 acpi_tables_size = addr - base_addr;
1083 BX_INFO("ACPI tables: RSDP addr=0x%08lx ACPI DATA addr=0x%08lx size=0x%x\n",
1084 (unsigned long)rsdp,
1085 (unsigned long)rsdt, acpi_tables_size);
1088 memset(rsdp, 0, sizeof(*rsdp));
1089 memcpy(rsdp->signature, "RSD PTR ", 8);
1090 #if (CONFIG_QEMU == 1)
1091 memcpy(rsdp->oem_id, "QEMU ", 6);
1093 memcpy(rsdp->oem_id, "BOCHS ", 6);
1095 rsdp->rsdt_physical_address = cpu_to_le32(rsdt_addr);
1096 rsdp->checksum = -checksum((void *)rsdp, 20);
1099 memset(rsdt, 0, sizeof(*rsdt));
1100 rsdt->table_offset_entry[0] = cpu_to_le32(fadt_addr);
1101 rsdt->table_offset_entry[1] = cpu_to_le32(madt_addr);
1102 rsdt->table_offset_entry[2] = cpu_to_le32(ssdt_addr);
1103 acpi_build_table_header((struct acpi_table_header *)rsdt,
1104 "RSDT", sizeof(*rsdt), 1);
1107 memset(fadt, 0, sizeof(*fadt));
1108 fadt->firmware_ctrl = cpu_to_le32(facs_addr);
1109 fadt->dsdt = cpu_to_le32(dsdt_addr);
1111 fadt->reserved1 = 0;
1112 fadt->sci_int = cpu_to_le16(pm_sci_int);
1113 fadt->smi_cmd = cpu_to_le32(SMI_CMD_IO_ADDR);
1114 fadt->acpi_enable = 0xf1;
1115 fadt->acpi_disable = 0xf0;
1116 fadt->pm1a_evt_blk = cpu_to_le32(pm_io_base);
1117 fadt->pm1a_cnt_blk = cpu_to_le32(pm_io_base + 0x04);
1118 fadt->pm_tmr_blk = cpu_to_le32(pm_io_base + 0x08);
1119 fadt->pm1_evt_len = 4;
1120 fadt->pm1_cnt_len = 2;
1121 fadt->pm_tmr_len = 4;
1122 fadt->plvl2_lat = cpu_to_le16(0xfff); // C2 state not supported
1123 fadt->plvl3_lat = cpu_to_le16(0xfff); // C3 state not supported
1124 /* WBINVD + PROC_C1 + PWR_BUTTON + SLP_BUTTON + FIX_RTC */
1125 fadt->flags = cpu_to_le32((1 << 0) | (1 << 2) | (1 << 4) | (1 << 5) | (1 << 6));
1126 acpi_build_table_header((struct acpi_table_header *)fadt, "FACP",
1130 memset(facs, 0, sizeof(*facs));
1131 memcpy(facs->signature, "FACS", 4);
1132 facs->length = cpu_to_le32(sizeof(*facs));
1135 memcpy(dsdt, AmlCode, sizeof(AmlCode));
1139 struct madt_processor_apic *apic;
1140 struct madt_io_apic *io_apic;
1142 memset(madt, 0, madt_size);
1143 madt->local_apic_address = cpu_to_le32(0xfee00000);
1144 madt->flags = cpu_to_le32(1);
1145 apic = (void *)(madt + 1);
1146 for(i=0;i<smp_cpus;i++) {
1147 apic->type = APIC_PROCESSOR;
1148 apic->length = sizeof(*apic);
1149 apic->processor_id = i;
1150 apic->local_apic_id = i;
1151 apic->flags = cpu_to_le32(1);
1154 io_apic = (void *)apic;
1155 io_apic->type = APIC_IO;
1156 io_apic->length = sizeof(*io_apic);
1157 io_apic->io_apic_id = smp_cpus;
1158 io_apic->address = cpu_to_le32(0xfec00000);
1159 io_apic->interrupt = cpu_to_le32(0);
1161 acpi_build_table_header((struct acpi_table_header *)madt,
1162 "APIC", madt_size, 1);
1166 /* SMBIOS entry point -- must be written to a 16-bit aligned address
1167 between 0xf0000 and 0xfffff.
1169 struct smbios_entry_point {
1170 char anchor_string[4];
1173 u8 smbios_major_version;
1174 u8 smbios_minor_version;
1175 u16 max_structure_size;
1176 u8 entry_point_revision;
1177 u8 formatted_area[5];
1178 char intermediate_anchor_string[5];
1179 u8 intermediate_checksum;
1180 u16 structure_table_length;
1181 u32 structure_table_address;
1182 u16 number_of_structures;
1183 u8 smbios_bcd_revision;
1184 } __attribute__((__packed__));
1186 /* This goes at the beginning of every SMBIOS structure. */
1187 struct smbios_structure_header {
1191 } __attribute__((__packed__));
1193 /* SMBIOS type 0 - BIOS Information */
1194 struct smbios_type_0 {
1195 struct smbios_structure_header header;
1197 u8 bios_version_str;
1198 u16 bios_starting_address_segment;
1199 u8 bios_release_date_str;
1201 u8 bios_characteristics[8];
1202 u8 bios_characteristics_extension_bytes[2];
1203 u8 system_bios_major_release;
1204 u8 system_bios_minor_release;
1205 u8 embedded_controller_major_release;
1206 u8 embedded_controller_minor_release;
1207 } __attribute__((__packed__));
1209 /* SMBIOS type 1 - System Information */
1210 struct smbios_type_1 {
1211 struct smbios_structure_header header;
1212 u8 manufacturer_str;
1213 u8 product_name_str;
1215 u8 serial_number_str;
1220 } __attribute__((__packed__));
1222 /* SMBIOS type 3 - System Enclosure (v2.3) */
1223 struct smbios_type_3 {
1224 struct smbios_structure_header header;
1225 u8 manufacturer_str;
1228 u8 serial_number_str;
1229 u8 asset_tag_number_str;
1231 u8 power_supply_state;
1236 u8 number_of_power_cords;
1237 u8 contained_element_count;
1238 // contained elements follow
1239 } __attribute__((__packed__));
1241 /* SMBIOS type 4 - Processor Information (v2.0) */
1242 struct smbios_type_4 {
1243 struct smbios_structure_header header;
1244 u8 socket_designation_str;
1246 u8 processor_family;
1247 u8 processor_manufacturer_str;
1248 u32 processor_id[2];
1249 u8 processor_version_str;
1255 u8 processor_upgrade;
1256 } __attribute__((__packed__));
1258 /* SMBIOS type 16 - Physical Memory Array
1259 * Associated with one type 17 (Memory Device).
1261 struct smbios_type_16 {
1262 struct smbios_structure_header header;
1265 u8 error_correction;
1266 u32 maximum_capacity;
1267 u16 memory_error_information_handle;
1268 u16 number_of_memory_devices;
1269 } __attribute__((__packed__));
1271 /* SMBIOS type 17 - Memory Device
1272 * Associated with one type 19
1274 struct smbios_type_17 {
1275 struct smbios_structure_header header;
1276 u16 physical_memory_array_handle;
1277 u16 memory_error_information_handle;
1283 u8 device_locator_str;
1284 u8 bank_locator_str;
1287 } __attribute__((__packed__));
1289 /* SMBIOS type 19 - Memory Array Mapped Address */
1290 struct smbios_type_19 {
1291 struct smbios_structure_header header;
1292 u32 starting_address;
1294 u16 memory_array_handle;
1296 } __attribute__((__packed__));
1298 /* SMBIOS type 20 - Memory Device Mapped Address */
1299 struct smbios_type_20 {
1300 struct smbios_structure_header header;
1301 u32 starting_address;
1303 u16 memory_device_handle;
1304 u16 memory_array_mapped_address_handle;
1305 u8 partition_row_position;
1306 u8 interleave_position;
1307 u8 interleaved_data_depth;
1308 } __attribute__((__packed__));
1310 /* SMBIOS type 32 - System Boot Information */
1311 struct smbios_type_32 {
1312 struct smbios_structure_header header;
1315 } __attribute__((__packed__));
1317 /* SMBIOS type 127 -- End-of-table */
1318 struct smbios_type_127 {
1319 struct smbios_structure_header header;
1320 } __attribute__((__packed__));
1323 smbios_entry_point_init(void *start,
1324 u16 max_structure_size,
1325 u16 structure_table_length,
1326 u32 structure_table_address,
1327 u16 number_of_structures)
1329 struct smbios_entry_point *ep = (struct smbios_entry_point *)start;
1331 memcpy(ep->anchor_string, "_SM_", 4);
1333 ep->smbios_major_version = 2;
1334 ep->smbios_minor_version = 4;
1335 ep->max_structure_size = max_structure_size;
1336 ep->entry_point_revision = 0;
1337 memset(ep->formatted_area, 0, 5);
1338 memcpy(ep->intermediate_anchor_string, "_DMI_", 5);
1340 ep->structure_table_length = structure_table_length;
1341 ep->structure_table_address = structure_table_address;
1342 ep->number_of_structures = number_of_structures;
1343 ep->smbios_bcd_revision = 0x24;
1346 ep->intermediate_checksum = 0;
1348 ep->checksum = -checksum(start, 0x10);
1350 ep->intermediate_checksum = -checksum(start + 0x10, ep->length - 0x10);
1353 /* Type 0 -- BIOS Information */
1354 #define RELEASE_DATE_STR "01/01/2007"
1356 smbios_type_0_init(void *start)
1358 struct smbios_type_0 *p = (struct smbios_type_0 *)start;
1361 p->header.length = sizeof(struct smbios_type_0);
1362 p->header.handle = 0;
1365 p->bios_version_str = 1;
1366 p->bios_starting_address_segment = 0xe800;
1367 p->bios_release_date_str = 2;
1368 p->bios_rom_size = 0; /* FIXME */
1370 memset(p->bios_characteristics, 0, 7);
1371 p->bios_characteristics[7] = 0x08; /* BIOS characteristics not supported */
1372 p->bios_characteristics_extension_bytes[0] = 0;
1373 p->bios_characteristics_extension_bytes[1] = 0;
1375 p->system_bios_major_release = 1;
1376 p->system_bios_minor_release = 0;
1377 p->embedded_controller_major_release = 0xff;
1378 p->embedded_controller_minor_release = 0xff;
1380 start += sizeof(struct smbios_type_0);
1381 memcpy((char *)start, CONFIG_APPNAME, sizeof(CONFIG_APPNAME));
1382 start += sizeof(CONFIG_APPNAME);
1383 memcpy((char *)start, RELEASE_DATE_STR, sizeof(RELEASE_DATE_STR));
1384 start += sizeof(RELEASE_DATE_STR);
1390 /* Type 1 -- System Information */
1392 smbios_type_1_init(void *start)
1394 struct smbios_type_1 *p = (struct smbios_type_1 *)start;
1396 p->header.length = sizeof(struct smbios_type_1);
1397 p->header.handle = 0x100;
1399 p->manufacturer_str = 0;
1400 p->product_name_str = 0;
1402 p->serial_number_str = 0;
1404 memcpy(p->uuid, bios_uuid, 16);
1406 p->wake_up_type = 0x06; /* power switch */
1407 p->sku_number_str = 0;
1410 start += sizeof(struct smbios_type_1);
1411 *((u16 *)start) = 0;
1416 /* Type 3 -- System Enclosure */
1418 smbios_type_3_init(void *start)
1420 struct smbios_type_3 *p = (struct smbios_type_3 *)start;
1423 p->header.length = sizeof(struct smbios_type_3);
1424 p->header.handle = 0x300;
1426 p->manufacturer_str = 0;
1427 p->type = 0x01; /* other */
1429 p->serial_number_str = 0;
1430 p->asset_tag_number_str = 0;
1431 p->boot_up_state = 0x03; /* safe */
1432 p->power_supply_state = 0x03; /* safe */
1433 p->thermal_state = 0x03; /* safe */
1434 p->security_status = 0x02; /* unknown */
1437 p->number_of_power_cords = 0;
1438 p->contained_element_count = 0;
1440 start += sizeof(struct smbios_type_3);
1441 *((u16 *)start) = 0;
1446 /* Type 4 -- Processor Information */
1448 smbios_type_4_init(void *start, unsigned int cpu_number)
1450 struct smbios_type_4 *p = (struct smbios_type_4 *)start;
1453 p->header.length = sizeof(struct smbios_type_4);
1454 p->header.handle = 0x400 + cpu_number;
1456 p->socket_designation_str = 1;
1457 p->processor_type = 0x03; /* CPU */
1458 p->processor_family = 0x01; /* other */
1459 p->processor_manufacturer_str = 0;
1461 p->processor_id[0] = cpuid_signature;
1462 p->processor_id[1] = cpuid_features;
1464 p->processor_version_str = 0;
1466 p->external_clock = 0;
1468 p->max_speed = 0; /* unknown */
1469 p->current_speed = 0; /* unknown */
1471 p->status = 0x41; /* socket populated, CPU enabled */
1472 p->processor_upgrade = 0x01; /* other */
1474 start += sizeof(struct smbios_type_4);
1476 memcpy((char *)start, "CPU " "\0" "" "\0" "", 7);
1477 ((char *)start)[4] = cpu_number + '0';
1482 /* Type 16 -- Physical Memory Array */
1484 smbios_type_16_init(void *start, u32 memsize)
1486 struct smbios_type_16 *p = (struct smbios_type_16*)start;
1488 p->header.type = 16;
1489 p->header.length = sizeof(struct smbios_type_16);
1490 p->header.handle = 0x1000;
1492 p->location = 0x01; /* other */
1493 p->use = 0x03; /* system memory */
1494 p->error_correction = 0x01; /* other */
1495 p->maximum_capacity = memsize * 1024;
1496 p->memory_error_information_handle = 0xfffe; /* none provided */
1497 p->number_of_memory_devices = 1;
1499 start += sizeof(struct smbios_type_16);
1500 *((u16 *)start) = 0;
1505 /* Type 17 -- Memory Device */
1507 smbios_type_17_init(void *start, u32 memory_size_mb)
1509 struct smbios_type_17 *p = (struct smbios_type_17 *)start;
1511 p->header.type = 17;
1512 p->header.length = sizeof(struct smbios_type_17);
1513 p->header.handle = 0x1100;
1515 p->physical_memory_array_handle = 0x1000;
1516 p->total_width = 64;
1518 /* truncate memory_size_mb to 16 bits and clear most significant
1519 bit [indicates size in MB] */
1520 p->size = (u16) memory_size_mb & 0x7fff;
1521 p->form_factor = 0x09; /* DIMM */
1523 p->device_locator_str = 1;
1524 p->bank_locator_str = 0;
1525 p->memory_type = 0x07; /* RAM */
1528 start += sizeof(struct smbios_type_17);
1529 memcpy((char *)start, "DIMM 1", 7);
1536 /* Type 19 -- Memory Array Mapped Address */
1538 smbios_type_19_init(void *start, u32 memory_size_mb)
1540 struct smbios_type_19 *p = (struct smbios_type_19 *)start;
1542 p->header.type = 19;
1543 p->header.length = sizeof(struct smbios_type_19);
1544 p->header.handle = 0x1300;
1546 p->starting_address = 0;
1547 p->ending_address = (memory_size_mb-1) * 1024;
1548 p->memory_array_handle = 0x1000;
1549 p->partition_width = 1;
1551 start += sizeof(struct smbios_type_19);
1552 *((u16 *)start) = 0;
1557 /* Type 20 -- Memory Device Mapped Address */
1559 smbios_type_20_init(void *start, u32 memory_size_mb)
1561 struct smbios_type_20 *p = (struct smbios_type_20 *)start;
1563 p->header.type = 20;
1564 p->header.length = sizeof(struct smbios_type_20);
1565 p->header.handle = 0x1400;
1567 p->starting_address = 0;
1568 p->ending_address = (memory_size_mb-1)*1024;
1569 p->memory_device_handle = 0x1100;
1570 p->memory_array_mapped_address_handle = 0x1300;
1571 p->partition_row_position = 1;
1572 p->interleave_position = 0;
1573 p->interleaved_data_depth = 0;
1575 start += sizeof(struct smbios_type_20);
1577 *((u16 *)start) = 0;
1581 /* Type 32 -- System Boot Information */
1583 smbios_type_32_init(void *start)
1585 struct smbios_type_32 *p = (struct smbios_type_32 *)start;
1587 p->header.type = 32;
1588 p->header.length = sizeof(struct smbios_type_32);
1589 p->header.handle = 0x2000;
1590 memset(p->reserved, 0, 6);
1591 p->boot_status = 0; /* no errors detected */
1593 start += sizeof(struct smbios_type_32);
1594 *((u16 *)start) = 0;
1599 /* Type 127 -- End of Table */
1601 smbios_type_127_init(void *start)
1603 struct smbios_type_127 *p = (struct smbios_type_127 *)start;
1605 p->header.type = 127;
1606 p->header.length = sizeof(struct smbios_type_127);
1607 p->header.handle = 0x7f00;
1609 start += sizeof(struct smbios_type_127);
1610 *((u16 *)start) = 0;
1615 void smbios_init(void)
1617 unsigned cpu_num, nr_structs = 0, max_struct_size = 0;
1618 char *start, *p, *q;
1619 int memsize = GET_EBDA(ram_size) / (1024 * 1024);
1621 #if (CONFIG_USE_EBDA_TABLES == 1)
1622 ebda_cur_addr = align(ebda_cur_addr, 16);
1623 start = (void *)(ebda_cur_addr);
1625 bios_table_cur_addr = align(bios_table_cur_addr, 16);
1626 start = (void *)(bios_table_cur_addr);
1629 p = (char *)start + sizeof(struct smbios_entry_point);
1631 #define add_struct(fn) { \
1634 if ((q - p) > max_struct_size) \
1635 max_struct_size = q - p; \
1639 add_struct(smbios_type_0_init(p));
1640 add_struct(smbios_type_1_init(p));
1641 add_struct(smbios_type_3_init(p));
1642 for (cpu_num = 1; cpu_num <= smp_cpus; cpu_num++)
1643 add_struct(smbios_type_4_init(p, cpu_num));
1644 add_struct(smbios_type_16_init(p, memsize));
1645 add_struct(smbios_type_17_init(p, memsize));
1646 add_struct(smbios_type_19_init(p, memsize));
1647 add_struct(smbios_type_20_init(p, memsize));
1648 add_struct(smbios_type_32_init(p));
1649 add_struct(smbios_type_127_init(p));
1653 smbios_entry_point_init(
1654 start, max_struct_size,
1655 (p - (char *)start) - sizeof(struct smbios_entry_point),
1656 (u32)(start + sizeof(struct smbios_entry_point)),
1659 #if (CONFIG_USE_EBDA_TABLES == 1)
1660 ebda_cur_addr += (p - (char *)start);
1662 bios_table_cur_addr += (p - (char *)start);
1665 BX_INFO("SMBIOS table addr=0x%08lx\n", (unsigned long)start);
1668 void rombios32_init(void)
1670 if (CONFIG_COREBOOT)
1671 // XXX - not supported on coreboot yet.
1674 BX_INFO("Starting rombios32\n");
1676 #if (CONFIG_USE_EBDA_TABLES == 1)
1677 ebda_cur_addr = ((*(u16 *)(0x40e)) << 4) + 0x380;
1678 BX_INFO("ebda_cur_addr: 0x%08lx\n", ebda_cur_addr);
1687 if (bios_table_cur_addr != 0) {
1698 bios_lock_shadow_ram();
1700 BX_INFO("bios_table_cur_addr: 0x%08lx\n", bios_table_cur_addr);
1701 if (bios_table_cur_addr > bios_table_end_addr)
1702 BX_PANIC("bios_table_end_addr overflow!\n");