1 /////////////////////////////////////////////////////////////////////////
3 // 32 bit Bochs BIOS init code
4 // Copyright (C) 2006 Fabrice Bellard
6 // This library is free software; you can redistribute it and/or
7 // modify it under the terms of the GNU Lesser General Public
8 // License as published by the Free Software Foundation; either
9 // version 2 of the License, or (at your option) any later version.
11 // This library is distributed in the hope that it will be useful,
12 // but WITHOUT ANY WARRANTY; without even the implied warranty of
13 // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 // Lesser General Public License for more details.
16 // You should have received a copy of the GNU Lesser General Public
17 // License along with this library; if not, write to the Free Software
18 // Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
20 #include "util.h" // dprintf
21 #include "pci.h" // PCIDevice
22 #include "types.h" // u32
23 #include "config.h" // CONFIG_*
24 #include "memmap.h" // bios_table_cur_addr
25 #include "acpi.h" // acpi_bios_init
27 #define cpuid(index, eax, ebx, ecx, edx) \
28 asm volatile ("cpuid" \
29 : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx) \
32 #define CPUID_APIC (1 << 9)
34 #define APIC_BASE ((u8 *)0xfee00000)
35 #define APIC_ICR_LOW 0x300
36 #define APIC_SVR 0x0F0
38 #define APIC_LVT3 0x370
40 #define APIC_ENABLED 0x0100
42 #define MPTABLE_MAX_SIZE 0x00002000
44 static inline void writel(void *addr, u32 val)
46 *(volatile u32 *)addr = val;
49 static inline void writew(void *addr, u16 val)
51 *(volatile u16 *)addr = val;
54 static inline void writeb(void *addr, u8 val)
56 *(volatile u8 *)addr = val;
59 static inline u32 readl(const void *addr)
61 return *(volatile const u32 *)addr;
64 static inline u16 readw(const void *addr)
66 return *(volatile const u16 *)addr;
69 static inline u8 readb(const void *addr)
71 return *(volatile const u8 *)addr;
77 u32 cpuid_ext_features;
79 #if (CONFIG_USE_EBDA_TABLES == 1)
80 unsigned long ebda_cur_addr;
85 #if (CONFIG_QEMU == 1)
86 u32 eax, ebx, ecx, edx;
88 // check if backdoor port exists
89 asm volatile ("outl %%eax, %%dx"
90 : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx)
91 : "a" (0x564d5868), "c" (0xa), "d" (0x5658));
92 if (ebx == 0x564d5868) {
93 u32 *uuid_ptr = (u32 *)bios_uuid;
95 asm volatile ("outl %%eax, %%dx"
96 : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx)
97 : "a" (0x564d5868), "c" (0x13), "d" (0x5658));
106 memset(bios_uuid, 0, 16);
112 u32 eax, ebx, ecx, edx;
113 cpuid(1, eax, ebx, ecx, edx);
114 cpuid_signature = eax;
115 cpuid_features = edx;
116 cpuid_ext_features = ecx;
119 /****************************************************/
122 extern u8 smp_ap_boot_code_start;
123 extern u8 smp_ap_boot_code_end;
125 /* find the number of CPUs by launching a SIPI to them */
128 u32 val, sipi_vector;
131 if (cpuid_features & CPUID_APIC) {
133 /* enable local APIC */
134 val = readl(APIC_BASE + APIC_SVR);
136 writel(APIC_BASE + APIC_SVR, val);
138 writew((void *)BUILD_CPU_COUNT_ADDR, 1);
139 /* copy AP boot code */
140 memcpy((void *)BUILD_AP_BOOT_ADDR, &smp_ap_boot_code_start,
141 &smp_ap_boot_code_end - &smp_ap_boot_code_start);
144 writel(APIC_BASE + APIC_ICR_LOW, 0x000C4500);
145 sipi_vector = BUILD_AP_BOOT_ADDR >> 12;
146 writel(APIC_BASE + APIC_ICR_LOW, 0x000C4600 | sipi_vector);
150 smp_cpus = readw((void *)BUILD_CPU_COUNT_ADDR);
152 dprintf(1, "Found %d cpu(s)\n", smp_cpus);
155 /****************************************************/
158 #define PCI_ADDRESS_SPACE_MEM 0x00
159 #define PCI_ADDRESS_SPACE_IO 0x01
160 #define PCI_ADDRESS_SPACE_MEM_PREFETCH 0x08
162 #define PCI_ROM_SLOT 6
163 #define PCI_NUM_REGIONS 7
165 #define PCI_DEVICES_MAX 64
167 static u32 pci_bios_io_addr;
168 static u32 pci_bios_mem_addr;
169 static u32 pci_bios_bigmem_addr;
170 /* host irqs corresponding to PCI irqs A-D */
171 static u8 pci_irqs[4] = { 11, 9, 11, 9 };
172 static PCIDevice i440_pcidev;
174 static void pci_set_io_region_addr(PCIDevice d, int region_num, u32 addr)
179 if ( region_num == PCI_ROM_SLOT ) {
182 ofs = 0x10 + region_num * 4;
185 old_addr = pci_config_readl(d, ofs);
187 pci_config_writel(d, ofs, addr);
188 dprintf(1, "region %d: 0x%08x\n", region_num, addr);
190 /* enable memory mappings */
191 cmd = pci_config_readw(d, PCI_COMMAND);
192 if ( region_num == PCI_ROM_SLOT )
194 else if (old_addr & PCI_ADDRESS_SPACE_IO)
198 pci_config_writew(d, PCI_COMMAND, cmd);
201 /* return the global irq number corresponding to a given device irq
202 pin. We could also use the bus number to have a more precise
204 static int pci_slot_get_pirq(PCIDevice pci_dev, int irq_num)
207 slot_addend = (pci_dev.devfn >> 3) - 1;
208 return (irq_num + slot_addend) & 3;
211 static void pci_bios_init_bridges(PCIDevice d)
213 u16 vendor_id, device_id;
215 vendor_id = pci_config_readw(d, PCI_VENDOR_ID);
216 device_id = pci_config_readw(d, PCI_DEVICE_ID);
218 if (vendor_id == 0x8086 && device_id == 0x7000) {
226 for(i = 0; i < 4; i++) {
228 /* set to trigger level */
229 elcr[irq >> 3] |= (1 << (irq & 7));
230 /* activate irq remapping in PIIX */
231 pci_config_writeb(d, 0x60 + i, irq);
233 outb(elcr[0], 0x4d0);
234 outb(elcr[1], 0x4d1);
235 dprintf(1, "PIIX3 init: elcr=%02x %02x\n",
237 } else if (vendor_id == 0x8086 && device_id == 0x1237) {
238 /* i440 PCI bridge */
244 ".globl smp_ap_boot_code_start\n"
245 ".globl smp_ap_boot_code_end\n"
246 ".global smm_relocation_start\n"
247 ".global smm_relocation_end\n"
248 ".global smm_code_start\n"
249 ".global smm_code_end\n"
252 "smp_ap_boot_code_start:\n"
255 " incw " __stringify(BUILD_CPU_COUNT_ADDR) "\n"
259 "smp_ap_boot_code_end:\n"
261 /* code to relocate SMBASE to 0xa0000 */
262 "smm_relocation_start:\n"
263 " mov $0x38000 + 0x7efc, %ebx\n"
264 " addr32 mov (%ebx), %al\n" /* revision ID to see if x86_64 or x86 */
267 " mov $0x38000 + 0x7ef8, %ebx\n"
270 " mov $0x38000 + 0x7f00, %ebx\n"
272 " movl $0xa0000, %eax\n"
273 " addr32 movl %eax, (%ebx)\n"
274 /* indicate to the BIOS that the SMM code was executed */
279 "smm_relocation_end:\n"
281 /* minimal SMM code to enable or disable ACPI */
289 " mov $" __stringify(BUILD_PM_IO_BASE) " + 0x04, %dx\n" /* PMCNTRL */
301 " mov $" __stringify(BUILD_PM_IO_BASE) " + 0x04, %dx\n" /* PMCNTRL */
312 extern u8 smm_relocation_start, smm_relocation_end;
313 extern u8 smm_code_start, smm_code_end;
315 #if (CONFIG_USE_SMM == 1)
316 static void smm_init(PCIDevice d)
320 /* check if SMM init is already done */
321 value = pci_config_readl(d, 0x58);
322 if ((value & (1 << 25)) == 0) {
324 /* copy the SMM relocation code */
325 memcpy((void *)0x38000, &smm_relocation_start,
326 &smm_relocation_end - &smm_relocation_start);
328 /* enable SMI generation when writing to the APMC register */
329 pci_config_writel(d, 0x58, value | (1 << 25));
331 /* init APM status port */
334 /* raise an SMI interrupt */
337 /* wait until SMM code executed */
338 while (inb(0xb3) != 0x00)
341 /* enable the SMM memory window */
342 pci_config_writeb(i440_pcidev, 0x72, 0x02 | 0x48);
344 /* copy the SMM code */
345 memcpy((void *)0xa8000, &smm_code_start,
346 &smm_code_end - &smm_code_start);
349 /* close the SMM memory window and enable normal SMM */
350 pci_config_writeb(i440_pcidev, 0x72, 0x02 | 0x08);
355 static void pci_bios_init_device(PCIDevice d)
359 int i, pin, pic_irq, vendor_id, device_id;
361 class = pci_config_readw(d, PCI_CLASS_DEVICE);
362 vendor_id = pci_config_readw(d, PCI_VENDOR_ID);
363 device_id = pci_config_readw(d, PCI_DEVICE_ID);
364 dprintf(1, "PCI: bus=%d devfn=0x%02x: vendor_id=0x%04x device_id=0x%04x\n",
365 d.bus, d.devfn, vendor_id, device_id);
368 if (vendor_id == 0x8086 && device_id == 0x7010) {
370 pci_config_writew(d, 0x40, 0x8000); // enable IDE0
371 pci_config_writew(d, 0x42, 0x8000); // enable IDE1
374 /* IDE: we map it as in ISA mode */
375 pci_set_io_region_addr(d, 0, 0x1f0);
376 pci_set_io_region_addr(d, 1, 0x3f4);
377 pci_set_io_region_addr(d, 2, 0x170);
378 pci_set_io_region_addr(d, 3, 0x374);
382 if (vendor_id != 0x1234)
384 /* VGA: map frame buffer to default Bochs VBE address */
385 pci_set_io_region_addr(d, 0, 0xE0000000);
389 if (vendor_id == 0x1014) {
391 if (device_id == 0x0046 || device_id == 0xFFFF) {
393 pci_set_io_region_addr(d, 0, 0x80800000 + 0x00040000);
398 if (vendor_id == 0x0106b &&
399 (device_id == 0x0017 || device_id == 0x0022)) {
401 pci_set_io_region_addr(d, 0, 0x80800000);
406 /* default memory mappings */
407 for(i = 0; i < PCI_NUM_REGIONS; i++) {
411 if (i == PCI_ROM_SLOT)
415 pci_config_writel(d, ofs, 0xffffffff);
416 val = pci_config_readl(d, ofs);
418 size = (~(val & ~0xf)) + 1;
419 if (val & PCI_ADDRESS_SPACE_IO)
420 paddr = &pci_bios_io_addr;
421 else if (size >= 0x04000000)
422 paddr = &pci_bios_bigmem_addr;
424 paddr = &pci_bios_mem_addr;
425 *paddr = (*paddr + size - 1) & ~(size - 1);
426 pci_set_io_region_addr(d, i, *paddr);
433 /* map the interrupt */
434 pin = pci_config_readb(d, PCI_INTERRUPT_PIN);
436 pin = pci_slot_get_pirq(d, pin - 1);
437 pic_irq = pci_irqs[pin];
438 pci_config_writeb(d, PCI_INTERRUPT_LINE, pic_irq);
441 if (vendor_id == 0x8086 && device_id == 0x7113) {
442 /* PIIX4 Power Management device (for ACPI) */
443 u32 pm_io_base = BUILD_PM_IO_BASE;
444 pci_config_writel(d, 0x40, pm_io_base | 1);
445 pci_config_writeb(d, 0x80, 0x01); /* enable PM io space */
446 u32 smb_io_base = BUILD_SMB_IO_BASE;
447 pci_config_writel(d, 0x90, smb_io_base | 1);
448 pci_config_writeb(d, 0xd2, 0x09); /* enable SMBus io space */
449 #if (CONFIG_USE_SMM == 1)
455 void pci_for_each_device(void (*init_func)(PCIDevice d))
458 u16 vendor_id, device_id;
460 for(bus = 0; bus < 1; bus++) {
461 for(devfn = 0; devfn < 256; devfn++) {
462 PCIDevice d = pci_bd(bus, devfn);
463 vendor_id = pci_config_readw(d, PCI_VENDOR_ID);
464 device_id = pci_config_readw(d, PCI_DEVICE_ID);
465 if (vendor_id != 0xffff || device_id != 0xffff) {
472 void pci_bios_init(void)
474 pci_bios_io_addr = 0xc000;
475 pci_bios_mem_addr = 0xf0000000;
476 pci_bios_bigmem_addr = GET_EBDA(ram_size);
477 if (pci_bios_bigmem_addr < 0x90000000)
478 pci_bios_bigmem_addr = 0x90000000;
480 pci_for_each_device(pci_bios_init_bridges);
482 pci_for_each_device(pci_bios_init_device);
485 /****************************************************/
486 /* Multi Processor table init */
488 static void putb(u8 **pp, int val)
496 static void putstr(u8 **pp, const char *str)
505 static void putle16(u8 **pp, int val)
514 static void putle32(u8 **pp, int val)
525 static void mptable_init(void)
527 u8 *mp_config_table, *q, *float_pointer_struct;
528 int ioapic_id, i, len;
529 int mp_config_table_size;
531 #if (CONFIG_QEMU == 1)
536 #if (CONFIG_USE_EBDA_TABLES == 1)
537 mp_config_table = (u8 *)(GET_EBDA(ram_size) - CONFIG_ACPI_DATA_SIZE
540 bios_table_cur_addr = ALIGN(bios_table_cur_addr, 16);
541 mp_config_table = (u8 *)bios_table_cur_addr;
544 putstr(&q, "PCMP"); /* "PCMP signature */
545 putle16(&q, 0); /* table length (patched later) */
546 putb(&q, 4); /* spec rev */
547 putb(&q, 0); /* checksum (patched later) */
548 #if (CONFIG_QEMU == 1)
549 putstr(&q, "QEMUCPU "); /* OEM id */
551 putstr(&q, "BOCHSCPU");
553 putstr(&q, "0.1 "); /* vendor id */
554 putle32(&q, 0); /* OEM table ptr */
555 putle16(&q, 0); /* OEM table size */
556 putle16(&q, smp_cpus + 18); /* entry count */
557 putle32(&q, 0xfee00000); /* local APIC addr */
558 putle16(&q, 0); /* ext table length */
559 putb(&q, 0); /* ext table checksum */
560 putb(&q, 0); /* reserved */
562 for(i = 0; i < smp_cpus; i++) {
563 putb(&q, 0); /* entry type = processor */
564 putb(&q, i); /* APIC id */
565 putb(&q, 0x11); /* local APIC version number */
567 putb(&q, 3); /* cpu flags: enabled, bootstrap cpu */
569 putb(&q, 1); /* cpu flags: enabled */
570 putb(&q, 0); /* cpu signature */
574 putle16(&q, 0x201); /* feature flags */
577 putle16(&q, 0); /* reserved */
584 putb(&q, 1); /* entry type = bus */
585 putb(&q, 0); /* bus ID */
589 ioapic_id = smp_cpus;
590 putb(&q, 2); /* entry type = I/O APIC */
591 putb(&q, ioapic_id); /* apic ID */
592 putb(&q, 0x11); /* I/O APIC version number */
593 putb(&q, 1); /* enable */
594 putle32(&q, 0xfec00000); /* I/O APIC addr */
597 for(i = 0; i < 16; i++) {
598 putb(&q, 3); /* entry type = I/O interrupt */
599 putb(&q, 0); /* interrupt type = vectored interrupt */
600 putb(&q, 0); /* flags: po=0, el=0 */
602 putb(&q, 0); /* source bus ID = ISA */
603 putb(&q, i); /* source bus IRQ */
604 putb(&q, ioapic_id); /* dest I/O APIC ID */
605 putb(&q, i); /* dest I/O APIC interrupt in */
608 len = q - mp_config_table;
609 mp_config_table[4] = len;
610 mp_config_table[5] = len >> 8;
612 mp_config_table[7] = -checksum(mp_config_table, q - mp_config_table);
614 mp_config_table_size = q - mp_config_table;
616 #if (CONFIG_USE_EBDA_TABLES != 1)
617 bios_table_cur_addr += mp_config_table_size;
620 /* floating pointer structure */
621 #if (CONFIG_USE_EBDA_TABLES == 1)
622 ebda_cur_addr = ALIGN(ebda_cur_addr, 16);
623 float_pointer_struct = (u8 *)ebda_cur_addr;
625 bios_table_cur_addr = ALIGN(bios_table_cur_addr, 16);
626 float_pointer_struct = (u8 *)bios_table_cur_addr;
628 q = float_pointer_struct;
630 /* pointer to MP config table */
631 putle32(&q, (unsigned long)mp_config_table);
633 putb(&q, 1); /* length in 16 byte units */
634 putb(&q, 4); /* MP spec revision */
635 putb(&q, 0); /* checksum (patched later) */
636 putb(&q, 0); /* MP feature byte 1 */
642 float_pointer_struct[10] = -checksum(float_pointer_struct
643 , q - float_pointer_struct);
644 #if (CONFIG_USE_EBDA_TABLES == 1)
645 ebda_cur_addr += (q - float_pointer_struct);
647 bios_table_cur_addr += (q - float_pointer_struct);
649 dprintf(1, "MP table addr=0x%08lx MPC table addr=0x%08lx size=0x%x\n",
650 (unsigned long)float_pointer_struct,
651 (unsigned long)mp_config_table,
652 mp_config_table_size);
655 /* SMBIOS entry point -- must be written to a 16-bit aligned address
656 between 0xf0000 and 0xfffff.
658 struct smbios_entry_point {
659 char anchor_string[4];
662 u8 smbios_major_version;
663 u8 smbios_minor_version;
664 u16 max_structure_size;
665 u8 entry_point_revision;
666 u8 formatted_area[5];
667 char intermediate_anchor_string[5];
668 u8 intermediate_checksum;
669 u16 structure_table_length;
670 u32 structure_table_address;
671 u16 number_of_structures;
672 u8 smbios_bcd_revision;
673 } __attribute__((__packed__));
675 /* This goes at the beginning of every SMBIOS structure. */
676 struct smbios_structure_header {
680 } __attribute__((__packed__));
682 /* SMBIOS type 0 - BIOS Information */
683 struct smbios_type_0 {
684 struct smbios_structure_header header;
687 u16 bios_starting_address_segment;
688 u8 bios_release_date_str;
690 u8 bios_characteristics[8];
691 u8 bios_characteristics_extension_bytes[2];
692 u8 system_bios_major_release;
693 u8 system_bios_minor_release;
694 u8 embedded_controller_major_release;
695 u8 embedded_controller_minor_release;
696 } __attribute__((__packed__));
698 /* SMBIOS type 1 - System Information */
699 struct smbios_type_1 {
700 struct smbios_structure_header header;
704 u8 serial_number_str;
709 } __attribute__((__packed__));
711 /* SMBIOS type 3 - System Enclosure (v2.3) */
712 struct smbios_type_3 {
713 struct smbios_structure_header header;
717 u8 serial_number_str;
718 u8 asset_tag_number_str;
720 u8 power_supply_state;
725 u8 number_of_power_cords;
726 u8 contained_element_count;
727 // contained elements follow
728 } __attribute__((__packed__));
730 /* SMBIOS type 4 - Processor Information (v2.0) */
731 struct smbios_type_4 {
732 struct smbios_structure_header header;
733 u8 socket_designation_str;
736 u8 processor_manufacturer_str;
738 u8 processor_version_str;
744 u8 processor_upgrade;
745 } __attribute__((__packed__));
747 /* SMBIOS type 16 - Physical Memory Array
748 * Associated with one type 17 (Memory Device).
750 struct smbios_type_16 {
751 struct smbios_structure_header header;
755 u32 maximum_capacity;
756 u16 memory_error_information_handle;
757 u16 number_of_memory_devices;
758 } __attribute__((__packed__));
760 /* SMBIOS type 17 - Memory Device
761 * Associated with one type 19
763 struct smbios_type_17 {
764 struct smbios_structure_header header;
765 u16 physical_memory_array_handle;
766 u16 memory_error_information_handle;
772 u8 device_locator_str;
776 } __attribute__((__packed__));
778 /* SMBIOS type 19 - Memory Array Mapped Address */
779 struct smbios_type_19 {
780 struct smbios_structure_header header;
781 u32 starting_address;
783 u16 memory_array_handle;
785 } __attribute__((__packed__));
787 /* SMBIOS type 20 - Memory Device Mapped Address */
788 struct smbios_type_20 {
789 struct smbios_structure_header header;
790 u32 starting_address;
792 u16 memory_device_handle;
793 u16 memory_array_mapped_address_handle;
794 u8 partition_row_position;
795 u8 interleave_position;
796 u8 interleaved_data_depth;
797 } __attribute__((__packed__));
799 /* SMBIOS type 32 - System Boot Information */
800 struct smbios_type_32 {
801 struct smbios_structure_header header;
804 } __attribute__((__packed__));
806 /* SMBIOS type 127 -- End-of-table */
807 struct smbios_type_127 {
808 struct smbios_structure_header header;
809 } __attribute__((__packed__));
812 smbios_entry_point_init(void *start,
813 u16 max_structure_size,
814 u16 structure_table_length,
815 u32 structure_table_address,
816 u16 number_of_structures)
818 struct smbios_entry_point *ep = (struct smbios_entry_point *)start;
820 memcpy(ep->anchor_string, "_SM_", 4);
822 ep->smbios_major_version = 2;
823 ep->smbios_minor_version = 4;
824 ep->max_structure_size = max_structure_size;
825 ep->entry_point_revision = 0;
826 memset(ep->formatted_area, 0, 5);
827 memcpy(ep->intermediate_anchor_string, "_DMI_", 5);
829 ep->structure_table_length = structure_table_length;
830 ep->structure_table_address = structure_table_address;
831 ep->number_of_structures = number_of_structures;
832 ep->smbios_bcd_revision = 0x24;
835 ep->intermediate_checksum = 0;
837 ep->checksum = -checksum(start, 0x10);
839 ep->intermediate_checksum = -checksum(start + 0x10, ep->length - 0x10);
842 /* Type 0 -- BIOS Information */
843 #define RELEASE_DATE_STR "01/01/2007"
845 smbios_type_0_init(void *start)
847 struct smbios_type_0 *p = (struct smbios_type_0 *)start;
850 p->header.length = sizeof(struct smbios_type_0);
851 p->header.handle = 0;
854 p->bios_version_str = 1;
855 p->bios_starting_address_segment = 0xe800;
856 p->bios_release_date_str = 2;
857 p->bios_rom_size = 0; /* FIXME */
859 memset(p->bios_characteristics, 0, 7);
860 p->bios_characteristics[7] = 0x08; /* BIOS characteristics not supported */
861 p->bios_characteristics_extension_bytes[0] = 0;
862 p->bios_characteristics_extension_bytes[1] = 0;
864 p->system_bios_major_release = 1;
865 p->system_bios_minor_release = 0;
866 p->embedded_controller_major_release = 0xff;
867 p->embedded_controller_minor_release = 0xff;
869 start += sizeof(struct smbios_type_0);
870 memcpy((char *)start, CONFIG_APPNAME, sizeof(CONFIG_APPNAME));
871 start += sizeof(CONFIG_APPNAME);
872 memcpy((char *)start, RELEASE_DATE_STR, sizeof(RELEASE_DATE_STR));
873 start += sizeof(RELEASE_DATE_STR);
879 /* Type 1 -- System Information */
881 smbios_type_1_init(void *start)
883 struct smbios_type_1 *p = (struct smbios_type_1 *)start;
885 p->header.length = sizeof(struct smbios_type_1);
886 p->header.handle = 0x100;
888 p->manufacturer_str = 0;
889 p->product_name_str = 0;
891 p->serial_number_str = 0;
893 memcpy(p->uuid, bios_uuid, 16);
895 p->wake_up_type = 0x06; /* power switch */
896 p->sku_number_str = 0;
899 start += sizeof(struct smbios_type_1);
905 /* Type 3 -- System Enclosure */
907 smbios_type_3_init(void *start)
909 struct smbios_type_3 *p = (struct smbios_type_3 *)start;
912 p->header.length = sizeof(struct smbios_type_3);
913 p->header.handle = 0x300;
915 p->manufacturer_str = 0;
916 p->type = 0x01; /* other */
918 p->serial_number_str = 0;
919 p->asset_tag_number_str = 0;
920 p->boot_up_state = 0x03; /* safe */
921 p->power_supply_state = 0x03; /* safe */
922 p->thermal_state = 0x03; /* safe */
923 p->security_status = 0x02; /* unknown */
926 p->number_of_power_cords = 0;
927 p->contained_element_count = 0;
929 start += sizeof(struct smbios_type_3);
935 /* Type 4 -- Processor Information */
937 smbios_type_4_init(void *start, unsigned int cpu_number)
939 struct smbios_type_4 *p = (struct smbios_type_4 *)start;
942 p->header.length = sizeof(struct smbios_type_4);
943 p->header.handle = 0x400 + cpu_number;
945 p->socket_designation_str = 1;
946 p->processor_type = 0x03; /* CPU */
947 p->processor_family = 0x01; /* other */
948 p->processor_manufacturer_str = 0;
950 p->processor_id[0] = cpuid_signature;
951 p->processor_id[1] = cpuid_features;
953 p->processor_version_str = 0;
955 p->external_clock = 0;
957 p->max_speed = 0; /* unknown */
958 p->current_speed = 0; /* unknown */
960 p->status = 0x41; /* socket populated, CPU enabled */
961 p->processor_upgrade = 0x01; /* other */
963 start += sizeof(struct smbios_type_4);
965 memcpy((char *)start, "CPU " "\0" "" "\0" "", 7);
966 ((char *)start)[4] = cpu_number + '0';
971 /* Type 16 -- Physical Memory Array */
973 smbios_type_16_init(void *start, u32 memsize)
975 struct smbios_type_16 *p = (struct smbios_type_16*)start;
978 p->header.length = sizeof(struct smbios_type_16);
979 p->header.handle = 0x1000;
981 p->location = 0x01; /* other */
982 p->use = 0x03; /* system memory */
983 p->error_correction = 0x01; /* other */
984 p->maximum_capacity = memsize * 1024;
985 p->memory_error_information_handle = 0xfffe; /* none provided */
986 p->number_of_memory_devices = 1;
988 start += sizeof(struct smbios_type_16);
994 /* Type 17 -- Memory Device */
996 smbios_type_17_init(void *start, u32 memory_size_mb)
998 struct smbios_type_17 *p = (struct smbios_type_17 *)start;
1000 p->header.type = 17;
1001 p->header.length = sizeof(struct smbios_type_17);
1002 p->header.handle = 0x1100;
1004 p->physical_memory_array_handle = 0x1000;
1005 p->total_width = 64;
1007 /* truncate memory_size_mb to 16 bits and clear most significant
1008 bit [indicates size in MB] */
1009 p->size = (u16) memory_size_mb & 0x7fff;
1010 p->form_factor = 0x09; /* DIMM */
1012 p->device_locator_str = 1;
1013 p->bank_locator_str = 0;
1014 p->memory_type = 0x07; /* RAM */
1017 start += sizeof(struct smbios_type_17);
1018 memcpy((char *)start, "DIMM 1", 7);
1025 /* Type 19 -- Memory Array Mapped Address */
1027 smbios_type_19_init(void *start, u32 memory_size_mb)
1029 struct smbios_type_19 *p = (struct smbios_type_19 *)start;
1031 p->header.type = 19;
1032 p->header.length = sizeof(struct smbios_type_19);
1033 p->header.handle = 0x1300;
1035 p->starting_address = 0;
1036 p->ending_address = (memory_size_mb-1) * 1024;
1037 p->memory_array_handle = 0x1000;
1038 p->partition_width = 1;
1040 start += sizeof(struct smbios_type_19);
1041 *((u16 *)start) = 0;
1046 /* Type 20 -- Memory Device Mapped Address */
1048 smbios_type_20_init(void *start, u32 memory_size_mb)
1050 struct smbios_type_20 *p = (struct smbios_type_20 *)start;
1052 p->header.type = 20;
1053 p->header.length = sizeof(struct smbios_type_20);
1054 p->header.handle = 0x1400;
1056 p->starting_address = 0;
1057 p->ending_address = (memory_size_mb-1)*1024;
1058 p->memory_device_handle = 0x1100;
1059 p->memory_array_mapped_address_handle = 0x1300;
1060 p->partition_row_position = 1;
1061 p->interleave_position = 0;
1062 p->interleaved_data_depth = 0;
1064 start += sizeof(struct smbios_type_20);
1066 *((u16 *)start) = 0;
1070 /* Type 32 -- System Boot Information */
1072 smbios_type_32_init(void *start)
1074 struct smbios_type_32 *p = (struct smbios_type_32 *)start;
1076 p->header.type = 32;
1077 p->header.length = sizeof(struct smbios_type_32);
1078 p->header.handle = 0x2000;
1079 memset(p->reserved, 0, 6);
1080 p->boot_status = 0; /* no errors detected */
1082 start += sizeof(struct smbios_type_32);
1083 *((u16 *)start) = 0;
1088 /* Type 127 -- End of Table */
1090 smbios_type_127_init(void *start)
1092 struct smbios_type_127 *p = (struct smbios_type_127 *)start;
1094 p->header.type = 127;
1095 p->header.length = sizeof(struct smbios_type_127);
1096 p->header.handle = 0x7f00;
1098 start += sizeof(struct smbios_type_127);
1099 *((u16 *)start) = 0;
1104 void smbios_init(void)
1106 unsigned cpu_num, nr_structs = 0, max_struct_size = 0;
1107 char *start, *p, *q;
1108 int memsize = GET_EBDA(ram_size) / (1024 * 1024);
1110 #if (CONFIG_USE_EBDA_TABLES == 1)
1111 ebda_cur_addr = ALIGN(ebda_cur_addr, 16);
1112 start = (void *)(ebda_cur_addr);
1114 bios_table_cur_addr = ALIGN(bios_table_cur_addr, 16);
1115 start = (void *)(bios_table_cur_addr);
1118 p = (char *)start + sizeof(struct smbios_entry_point);
1120 #define add_struct(fn) { \
1123 if ((q - p) > max_struct_size) \
1124 max_struct_size = q - p; \
1128 add_struct(smbios_type_0_init(p));
1129 add_struct(smbios_type_1_init(p));
1130 add_struct(smbios_type_3_init(p));
1131 for (cpu_num = 1; cpu_num <= smp_cpus; cpu_num++)
1132 add_struct(smbios_type_4_init(p, cpu_num));
1133 add_struct(smbios_type_16_init(p, memsize));
1134 add_struct(smbios_type_17_init(p, memsize));
1135 add_struct(smbios_type_19_init(p, memsize));
1136 add_struct(smbios_type_20_init(p, memsize));
1137 add_struct(smbios_type_32_init(p));
1138 add_struct(smbios_type_127_init(p));
1142 smbios_entry_point_init(
1143 start, max_struct_size,
1144 (p - (char *)start) - sizeof(struct smbios_entry_point),
1145 (u32)(start + sizeof(struct smbios_entry_point)),
1148 #if (CONFIG_USE_EBDA_TABLES == 1)
1149 ebda_cur_addr += (p - (char *)start);
1151 bios_table_cur_addr += (p - (char *)start);
1154 dprintf(1, "SMBIOS table addr=0x%08lx\n", (unsigned long)start);
1157 void rombios32_init(void)
1159 if (CONFIG_COREBOOT)
1160 // XXX - not supported on coreboot yet.
1163 dprintf(1, "Starting rombios32\n");
1165 #if (CONFIG_USE_EBDA_TABLES == 1)
1166 ebda_cur_addr = ((*(u16 *)(0x40e)) << 4) + 0x380;
1167 dprintf(1, "ebda_cur_addr: 0x%08lx\n", ebda_cur_addr);
1176 if (bios_table_cur_addr != 0) {
1186 dprintf(1, "bios_table_cur_addr: 0x%08x\n", bios_table_cur_addr);
1187 if (bios_table_cur_addr > bios_table_end_addr)
1188 BX_PANIC("bios_table_end_addr overflow!\n");