1 /////////////////////////////////////////////////////////////////////////
3 // 32 bit Bochs BIOS init code
4 // Copyright (C) 2006 Fabrice Bellard
6 // This library is free software; you can redistribute it and/or
7 // modify it under the terms of the GNU Lesser General Public
8 // License as published by the Free Software Foundation; either
9 // version 2 of the License, or (at your option) any later version.
11 // This library is distributed in the hope that it will be useful,
12 // but WITHOUT ANY WARRANTY; without even the implied warranty of
13 // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 // Lesser General Public License for more details.
16 // You should have received a copy of the GNU Lesser General Public
17 // License along with this library; if not, write to the Free Software
18 // Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
20 #include "util.h" // dprintf
21 #include "pci.h" // PCIDevice
22 #include "types.h" // u32
23 #include "config.h" // CONFIG_*
25 // Memory addresses used by this code. (Note global variables (bss)
27 #define CPU_COUNT_ADDR 0xf000
28 #define AP_BOOT_ADDR 0x10000
30 #define PM_IO_BASE 0xb000
31 #define SMB_IO_BASE 0xb100
33 #define cpuid(index, eax, ebx, ecx, edx) \
34 asm volatile ("cpuid" \
35 : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx) \
38 #define CPUID_APIC (1 << 9)
40 #define APIC_BASE ((u8 *)0xfee00000)
41 #define APIC_ICR_LOW 0x300
42 #define APIC_SVR 0x0F0
44 #define APIC_LVT3 0x370
46 #define APIC_ENABLED 0x0100
48 #define MPTABLE_MAX_SIZE 0x00002000
49 #define SMI_CMD_IO_ADDR 0xb2
51 static inline void writel(void *addr, u32 val)
53 *(volatile u32 *)addr = val;
56 static inline void writew(void *addr, u16 val)
58 *(volatile u16 *)addr = val;
61 static inline void writeb(void *addr, u8 val)
63 *(volatile u8 *)addr = val;
66 static inline u32 readl(const void *addr)
68 return *(volatile const u32 *)addr;
71 static inline u16 readw(const void *addr)
73 return *(volatile const u16 *)addr;
76 static inline u8 readb(const void *addr)
78 return *(volatile const u8 *)addr;
84 u32 cpuid_ext_features;
86 #if (CONFIG_USE_EBDA_TABLES == 1)
87 unsigned long ebda_cur_addr;
90 u32 pm_io_base, smb_io_base;
92 unsigned long bios_table_cur_addr;
93 unsigned long bios_table_end_addr;
97 #if (CONFIG_QEMU == 1)
98 u32 eax, ebx, ecx, edx;
100 // check if backdoor port exists
101 asm volatile ("outl %%eax, %%dx"
102 : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx)
103 : "a" (0x564d5868), "c" (0xa), "d" (0x5658));
104 if (ebx == 0x564d5868) {
105 u32 *uuid_ptr = (u32 *)bios_uuid;
107 asm volatile ("outl %%eax, %%dx"
108 : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx)
109 : "a" (0x564d5868), "c" (0x13), "d" (0x5658));
118 memset(bios_uuid, 0, 16);
124 u32 eax, ebx, ecx, edx;
125 cpuid(1, eax, ebx, ecx, edx);
126 cpuid_signature = eax;
127 cpuid_features = edx;
128 cpuid_ext_features = ecx;
131 /****************************************************/
134 extern u8 smp_ap_boot_code_start;
135 extern u8 smp_ap_boot_code_end;
137 /* find the number of CPUs by launching a SIPI to them */
140 u32 val, sipi_vector;
143 if (cpuid_features & CPUID_APIC) {
145 /* enable local APIC */
146 val = readl(APIC_BASE + APIC_SVR);
148 writel(APIC_BASE + APIC_SVR, val);
150 writew((void *)CPU_COUNT_ADDR, 1);
151 /* copy AP boot code */
152 memcpy((void *)AP_BOOT_ADDR, &smp_ap_boot_code_start,
153 &smp_ap_boot_code_end - &smp_ap_boot_code_start);
156 writel(APIC_BASE + APIC_ICR_LOW, 0x000C4500);
157 sipi_vector = AP_BOOT_ADDR >> 12;
158 writel(APIC_BASE + APIC_ICR_LOW, 0x000C4600 | sipi_vector);
162 smp_cpus = readw((void *)CPU_COUNT_ADDR);
164 dprintf(1, "Found %d cpu(s)\n", smp_cpus);
167 /****************************************************/
170 #define PCI_ADDRESS_SPACE_MEM 0x00
171 #define PCI_ADDRESS_SPACE_IO 0x01
172 #define PCI_ADDRESS_SPACE_MEM_PREFETCH 0x08
174 #define PCI_ROM_SLOT 6
175 #define PCI_NUM_REGIONS 7
177 #define PCI_DEVICES_MAX 64
179 #define PCI_VENDOR_ID 0x00 /* 16 bits */
180 #define PCI_DEVICE_ID 0x02 /* 16 bits */
181 #define PCI_COMMAND 0x04 /* 16 bits */
182 #define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
183 #define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
184 #define PCI_CLASS_DEVICE 0x0a /* Device class */
185 #define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
186 #define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
187 #define PCI_MIN_GNT 0x3e /* 8 bits */
188 #define PCI_MAX_LAT 0x3f /* 8 bits */
190 static u32 pci_bios_io_addr;
191 static u32 pci_bios_mem_addr;
192 static u32 pci_bios_bigmem_addr;
193 /* host irqs corresponding to PCI irqs A-D */
194 static u8 pci_irqs[4] = { 11, 9, 11, 9 };
195 static PCIDevice i440_pcidev;
197 static void pci_set_io_region_addr(PCIDevice d, int region_num, u32 addr)
202 if ( region_num == PCI_ROM_SLOT ) {
205 ofs = 0x10 + region_num * 4;
208 old_addr = pci_config_readl(d, ofs);
210 pci_config_writel(d, ofs, addr);
211 dprintf(1, "region %d: 0x%08x\n", region_num, addr);
213 /* enable memory mappings */
214 cmd = pci_config_readw(d, PCI_COMMAND);
215 if ( region_num == PCI_ROM_SLOT )
217 else if (old_addr & PCI_ADDRESS_SPACE_IO)
221 pci_config_writew(d, PCI_COMMAND, cmd);
224 /* return the global irq number corresponding to a given device irq
225 pin. We could also use the bus number to have a more precise
227 static int pci_slot_get_pirq(PCIDevice pci_dev, int irq_num)
230 slot_addend = (pci_dev.devfn >> 3) - 1;
231 return (irq_num + slot_addend) & 3;
234 static void pci_bios_init_bridges(PCIDevice d)
236 u16 vendor_id, device_id;
238 vendor_id = pci_config_readw(d, PCI_VENDOR_ID);
239 device_id = pci_config_readw(d, PCI_DEVICE_ID);
241 if (vendor_id == 0x8086 && device_id == 0x7000) {
249 for(i = 0; i < 4; i++) {
251 /* set to trigger level */
252 elcr[irq >> 3] |= (1 << (irq & 7));
253 /* activate irq remapping in PIIX */
254 pci_config_writeb(d, 0x60 + i, irq);
256 outb(elcr[0], 0x4d0);
257 outb(elcr[1], 0x4d1);
258 dprintf(1, "PIIX3 init: elcr=%02x %02x\n",
260 } else if (vendor_id == 0x8086 && device_id == 0x1237) {
261 /* i440 PCI bridge */
267 ".globl smp_ap_boot_code_start\n"
268 ".globl smp_ap_boot_code_end\n"
269 ".global smm_relocation_start\n"
270 ".global smm_relocation_end\n"
271 ".global smm_code_start\n"
272 ".global smm_code_end\n"
275 "smp_ap_boot_code_start:\n"
278 " incw " __stringify(CPU_COUNT_ADDR) "\n"
282 "smp_ap_boot_code_end:\n"
284 /* code to relocate SMBASE to 0xa0000 */
285 "smm_relocation_start:\n"
286 " mov $0x38000 + 0x7efc, %ebx\n"
287 " addr32 mov (%ebx), %al\n" /* revision ID to see if x86_64 or x86 */
290 " mov $0x38000 + 0x7ef8, %ebx\n"
293 " mov $0x38000 + 0x7f00, %ebx\n"
295 " movl $0xa0000, %eax\n"
296 " addr32 movl %eax, (%ebx)\n"
297 /* indicate to the BIOS that the SMM code was executed */
302 "smm_relocation_end:\n"
304 /* minimal SMM code to enable or disable ACPI */
312 " mov $" __stringify(PM_IO_BASE) " + 0x04, %dx\n" /* PMCNTRL */
324 " mov $" __stringify(PM_IO_BASE) " + 0x04, %dx\n" /* PMCNTRL */
335 extern u8 smm_relocation_start, smm_relocation_end;
336 extern u8 smm_code_start, smm_code_end;
338 #if (CONFIG_USE_SMM == 1)
339 static void smm_init(PCIDevice d)
343 /* check if SMM init is already done */
344 value = pci_config_readl(d, 0x58);
345 if ((value & (1 << 25)) == 0) {
347 /* copy the SMM relocation code */
348 memcpy((void *)0x38000, &smm_relocation_start,
349 &smm_relocation_end - &smm_relocation_start);
351 /* enable SMI generation when writing to the APMC register */
352 pci_config_writel(d, 0x58, value | (1 << 25));
354 /* init APM status port */
357 /* raise an SMI interrupt */
360 /* wait until SMM code executed */
361 while (inb(0xb3) != 0x00)
364 /* enable the SMM memory window */
365 pci_config_writeb(i440_pcidev, 0x72, 0x02 | 0x48);
367 /* copy the SMM code */
368 memcpy((void *)0xa8000, &smm_code_start,
369 &smm_code_end - &smm_code_start);
372 /* close the SMM memory window and enable normal SMM */
373 pci_config_writeb(i440_pcidev, 0x72, 0x02 | 0x08);
378 static void pci_bios_init_device(PCIDevice d)
382 int i, pin, pic_irq, vendor_id, device_id;
384 class = pci_config_readw(d, PCI_CLASS_DEVICE);
385 vendor_id = pci_config_readw(d, PCI_VENDOR_ID);
386 device_id = pci_config_readw(d, PCI_DEVICE_ID);
387 dprintf(1, "PCI: bus=%d devfn=0x%02x: vendor_id=0x%04x device_id=0x%04x\n",
388 d.bus, d.devfn, vendor_id, device_id);
391 if (vendor_id == 0x8086 && device_id == 0x7010) {
393 pci_config_writew(d, 0x40, 0x8000); // enable IDE0
394 pci_config_writew(d, 0x42, 0x8000); // enable IDE1
397 /* IDE: we map it as in ISA mode */
398 pci_set_io_region_addr(d, 0, 0x1f0);
399 pci_set_io_region_addr(d, 1, 0x3f4);
400 pci_set_io_region_addr(d, 2, 0x170);
401 pci_set_io_region_addr(d, 3, 0x374);
405 if (vendor_id != 0x1234)
407 /* VGA: map frame buffer to default Bochs VBE address */
408 pci_set_io_region_addr(d, 0, 0xE0000000);
412 if (vendor_id == 0x1014) {
414 if (device_id == 0x0046 || device_id == 0xFFFF) {
416 pci_set_io_region_addr(d, 0, 0x80800000 + 0x00040000);
421 if (vendor_id == 0x0106b &&
422 (device_id == 0x0017 || device_id == 0x0022)) {
424 pci_set_io_region_addr(d, 0, 0x80800000);
429 /* default memory mappings */
430 for(i = 0; i < PCI_NUM_REGIONS; i++) {
434 if (i == PCI_ROM_SLOT)
438 pci_config_writel(d, ofs, 0xffffffff);
439 val = pci_config_readl(d, ofs);
441 size = (~(val & ~0xf)) + 1;
442 if (val & PCI_ADDRESS_SPACE_IO)
443 paddr = &pci_bios_io_addr;
444 else if (size >= 0x04000000)
445 paddr = &pci_bios_bigmem_addr;
447 paddr = &pci_bios_mem_addr;
448 *paddr = (*paddr + size - 1) & ~(size - 1);
449 pci_set_io_region_addr(d, i, *paddr);
456 /* map the interrupt */
457 pin = pci_config_readb(d, PCI_INTERRUPT_PIN);
459 pin = pci_slot_get_pirq(d, pin - 1);
460 pic_irq = pci_irqs[pin];
461 pci_config_writeb(d, PCI_INTERRUPT_LINE, pic_irq);
464 if (vendor_id == 0x8086 && device_id == 0x7113) {
465 /* PIIX4 Power Management device (for ACPI) */
466 pm_io_base = PM_IO_BASE;
467 pci_config_writel(d, 0x40, pm_io_base | 1);
468 pci_config_writeb(d, 0x80, 0x01); /* enable PM io space */
469 smb_io_base = SMB_IO_BASE;
470 pci_config_writel(d, 0x90, smb_io_base | 1);
471 pci_config_writeb(d, 0xd2, 0x09); /* enable SMBus io space */
472 pm_sci_int = pci_config_readb(d, PCI_INTERRUPT_LINE);
473 #if (CONFIG_USE_SMM == 1)
480 void pci_for_each_device(void (*init_func)(PCIDevice d))
483 u16 vendor_id, device_id;
485 for(bus = 0; bus < 1; bus++) {
486 for(devfn = 0; devfn < 256; devfn++) {
487 PCIDevice d = pci_bd(bus, devfn);
488 vendor_id = pci_config_readw(d, PCI_VENDOR_ID);
489 device_id = pci_config_readw(d, PCI_DEVICE_ID);
490 if (vendor_id != 0xffff || device_id != 0xffff) {
497 void pci_bios_init(void)
499 pci_bios_io_addr = 0xc000;
500 pci_bios_mem_addr = 0xf0000000;
501 pci_bios_bigmem_addr = GET_EBDA(ram_size);
502 if (pci_bios_bigmem_addr < 0x90000000)
503 pci_bios_bigmem_addr = 0x90000000;
505 pci_for_each_device(pci_bios_init_bridges);
507 pci_for_each_device(pci_bios_init_device);
510 /****************************************************/
511 /* Multi Processor table init */
513 static void putb(u8 **pp, int val)
521 static void putstr(u8 **pp, const char *str)
530 static void putle16(u8 **pp, int val)
539 static void putle32(u8 **pp, int val)
550 static unsigned long align(unsigned long addr, unsigned long v)
552 return (addr + v - 1) & ~(v - 1);
555 static void mptable_init(void)
557 u8 *mp_config_table, *q, *float_pointer_struct;
558 int ioapic_id, i, len;
559 int mp_config_table_size;
561 #if (CONFIG_QEMU == 1)
566 #if (CONFIG_USE_EBDA_TABLES == 1)
567 mp_config_table = (u8 *)(GET_EBDA(ram_size) - CONFIG_ACPI_DATA_SIZE
570 bios_table_cur_addr = align(bios_table_cur_addr, 16);
571 mp_config_table = (u8 *)bios_table_cur_addr;
574 putstr(&q, "PCMP"); /* "PCMP signature */
575 putle16(&q, 0); /* table length (patched later) */
576 putb(&q, 4); /* spec rev */
577 putb(&q, 0); /* checksum (patched later) */
578 #if (CONFIG_QEMU == 1)
579 putstr(&q, "QEMUCPU "); /* OEM id */
581 putstr(&q, "BOCHSCPU");
583 putstr(&q, "0.1 "); /* vendor id */
584 putle32(&q, 0); /* OEM table ptr */
585 putle16(&q, 0); /* OEM table size */
586 putle16(&q, smp_cpus + 18); /* entry count */
587 putle32(&q, 0xfee00000); /* local APIC addr */
588 putle16(&q, 0); /* ext table length */
589 putb(&q, 0); /* ext table checksum */
590 putb(&q, 0); /* reserved */
592 for(i = 0; i < smp_cpus; i++) {
593 putb(&q, 0); /* entry type = processor */
594 putb(&q, i); /* APIC id */
595 putb(&q, 0x11); /* local APIC version number */
597 putb(&q, 3); /* cpu flags: enabled, bootstrap cpu */
599 putb(&q, 1); /* cpu flags: enabled */
600 putb(&q, 0); /* cpu signature */
604 putle16(&q, 0x201); /* feature flags */
607 putle16(&q, 0); /* reserved */
614 putb(&q, 1); /* entry type = bus */
615 putb(&q, 0); /* bus ID */
619 ioapic_id = smp_cpus;
620 putb(&q, 2); /* entry type = I/O APIC */
621 putb(&q, ioapic_id); /* apic ID */
622 putb(&q, 0x11); /* I/O APIC version number */
623 putb(&q, 1); /* enable */
624 putle32(&q, 0xfec00000); /* I/O APIC addr */
627 for(i = 0; i < 16; i++) {
628 putb(&q, 3); /* entry type = I/O interrupt */
629 putb(&q, 0); /* interrupt type = vectored interrupt */
630 putb(&q, 0); /* flags: po=0, el=0 */
632 putb(&q, 0); /* source bus ID = ISA */
633 putb(&q, i); /* source bus IRQ */
634 putb(&q, ioapic_id); /* dest I/O APIC ID */
635 putb(&q, i); /* dest I/O APIC interrupt in */
638 len = q - mp_config_table;
639 mp_config_table[4] = len;
640 mp_config_table[5] = len >> 8;
642 mp_config_table[7] = -checksum(mp_config_table, q - mp_config_table);
644 mp_config_table_size = q - mp_config_table;
646 #if (CONFIG_USE_EBDA_TABLES != 1)
647 bios_table_cur_addr += mp_config_table_size;
650 /* floating pointer structure */
651 #if (CONFIG_USE_EBDA_TABLES == 1)
652 ebda_cur_addr = align(ebda_cur_addr, 16);
653 float_pointer_struct = (u8 *)ebda_cur_addr;
655 bios_table_cur_addr = align(bios_table_cur_addr, 16);
656 float_pointer_struct = (u8 *)bios_table_cur_addr;
658 q = float_pointer_struct;
660 /* pointer to MP config table */
661 putle32(&q, (unsigned long)mp_config_table);
663 putb(&q, 1); /* length in 16 byte units */
664 putb(&q, 4); /* MP spec revision */
665 putb(&q, 0); /* checksum (patched later) */
666 putb(&q, 0); /* MP feature byte 1 */
672 float_pointer_struct[10] = -checksum(float_pointer_struct
673 , q - float_pointer_struct);
674 #if (CONFIG_USE_EBDA_TABLES == 1)
675 ebda_cur_addr += (q - float_pointer_struct);
677 bios_table_cur_addr += (q - float_pointer_struct);
679 dprintf(1, "MP table addr=0x%08lx MPC table addr=0x%08lx size=0x%x\n",
680 (unsigned long)float_pointer_struct,
681 (unsigned long)mp_config_table,
682 mp_config_table_size);
685 /****************************************************/
686 /* ACPI tables init */
688 /* Table structure from Linux kernel (the ACPI tables are under the
691 #define ACPI_TABLE_HEADER_DEF /* ACPI common table header */ \
692 u8 signature [4]; /* ACPI signature (4 ASCII characters) */\
693 u32 length; /* Length of table, in bytes, including header */\
694 u8 revision; /* ACPI Specification minor version # */\
695 u8 checksum; /* To make sum of entire table == 0 */\
696 u8 oem_id [6]; /* OEM identification */\
697 u8 oem_table_id [8]; /* OEM table identification */\
698 u32 oem_revision; /* OEM revision number */\
699 u8 asl_compiler_id [4]; /* ASL compiler vendor ID */\
700 u32 asl_compiler_revision; /* ASL compiler revision number */
703 struct acpi_table_header /* ACPI common table header */
705 ACPI_TABLE_HEADER_DEF
708 struct rsdp_descriptor /* Root System Descriptor Pointer */
710 u8 signature [8]; /* ACPI signature, contains "RSD PTR " */
711 u8 checksum; /* To make sum of struct == 0 */
712 u8 oem_id [6]; /* OEM identification */
713 u8 revision; /* Must be 0 for 1.0, 2 for 2.0 */
714 u32 rsdt_physical_address; /* 32-bit physical address of RSDT */
715 u32 length; /* XSDT Length in bytes including hdr */
716 u64 xsdt_physical_address; /* 64-bit physical address of XSDT */
717 u8 extended_checksum; /* Checksum of entire table */
718 u8 reserved [3]; /* Reserved field must be 0 */
722 * ACPI 1.0 Root System Description Table (RSDT)
724 struct rsdt_descriptor_rev1
726 ACPI_TABLE_HEADER_DEF /* ACPI common table header */
727 u32 table_offset_entry [3]; /* Array of pointers to other */
732 * ACPI 1.0 Firmware ACPI Control Structure (FACS)
734 struct facs_descriptor_rev1
736 u8 signature[4]; /* ACPI Signature */
737 u32 length; /* Length of structure, in bytes */
738 u32 hardware_signature; /* Hardware configuration signature */
739 u32 firmware_waking_vector; /* ACPI OS waking vector */
740 u32 global_lock; /* Global Lock */
741 u32 S4bios_f : 1; /* Indicates if S4BIOS support is present */
742 u32 reserved1 : 31; /* Must be 0 */
743 u8 resverved3 [40]; /* Reserved - must be zero */
748 * ACPI 1.0 Fixed ACPI Description Table (FADT)
750 struct fadt_descriptor_rev1
752 ACPI_TABLE_HEADER_DEF /* ACPI common table header */
753 u32 firmware_ctrl; /* Physical address of FACS */
754 u32 dsdt; /* Physical address of DSDT */
755 u8 model; /* System Interrupt Model */
756 u8 reserved1; /* Reserved */
757 u16 sci_int; /* System vector of SCI interrupt */
758 u32 smi_cmd; /* Port address of SMI command port */
759 u8 acpi_enable; /* Value to write to smi_cmd to enable ACPI */
760 u8 acpi_disable; /* Value to write to smi_cmd to disable ACPI */
761 u8 S4bios_req; /* Value to write to SMI CMD to enter S4BIOS state */
762 u8 reserved2; /* Reserved - must be zero */
763 u32 pm1a_evt_blk; /* Port address of Power Mgt 1a acpi_event Reg Blk */
764 u32 pm1b_evt_blk; /* Port address of Power Mgt 1b acpi_event Reg Blk */
765 u32 pm1a_cnt_blk; /* Port address of Power Mgt 1a Control Reg Blk */
766 u32 pm1b_cnt_blk; /* Port address of Power Mgt 1b Control Reg Blk */
767 u32 pm2_cnt_blk; /* Port address of Power Mgt 2 Control Reg Blk */
768 u32 pm_tmr_blk; /* Port address of Power Mgt Timer Ctrl Reg Blk */
769 u32 gpe0_blk; /* Port addr of General Purpose acpi_event 0 Reg Blk */
770 u32 gpe1_blk; /* Port addr of General Purpose acpi_event 1 Reg Blk */
771 u8 pm1_evt_len; /* Byte length of ports at pm1_x_evt_blk */
772 u8 pm1_cnt_len; /* Byte length of ports at pm1_x_cnt_blk */
773 u8 pm2_cnt_len; /* Byte Length of ports at pm2_cnt_blk */
774 u8 pm_tmr_len; /* Byte Length of ports at pm_tm_blk */
775 u8 gpe0_blk_len; /* Byte Length of ports at gpe0_blk */
776 u8 gpe1_blk_len; /* Byte Length of ports at gpe1_blk */
777 u8 gpe1_base; /* Offset in gpe model where gpe1 events start */
778 u8 reserved3; /* Reserved */
779 u16 plvl2_lat; /* Worst case HW latency to enter/exit C2 state */
780 u16 plvl3_lat; /* Worst case HW latency to enter/exit C3 state */
781 u16 flush_size; /* Size of area read to flush caches */
782 u16 flush_stride; /* Stride used in flushing caches */
783 u8 duty_offset; /* Bit location of duty cycle field in p_cnt reg */
784 u8 duty_width; /* Bit width of duty cycle field in p_cnt reg */
785 u8 day_alrm; /* Index to day-of-month alarm in RTC CMOS RAM */
786 u8 mon_alrm; /* Index to month-of-year alarm in RTC CMOS RAM */
787 u8 century; /* Index to century in RTC CMOS RAM */
788 u8 reserved4; /* Reserved */
789 u8 reserved4a; /* Reserved */
790 u8 reserved4b; /* Reserved */
792 u32 wb_invd : 1; /* The wbinvd instruction works properly */
793 u32 wb_invd_flush : 1; /* The wbinvd flushes but does not invalidate */
794 u32 proc_c1 : 1; /* All processors support C1 state */
795 u32 plvl2_up : 1; /* C2 state works on MP system */
796 u32 pwr_button : 1; /* Power button is handled as a generic feature */
797 u32 sleep_button : 1; /* Sleep button is handled as a generic feature, or not present */
798 u32 fixed_rTC : 1; /* RTC wakeup stat not in fixed register space */
799 u32 rtcs4 : 1; /* RTC wakeup stat not possible from S4 */
800 u32 tmr_val_ext : 1; /* The tmr_val width is 32 bits (0 = 24 bits) */
801 u32 reserved5 : 23; /* Reserved - must be zero */
808 * MADT values and structures
811 /* Values for MADT PCATCompat */
814 #define MULTIPLE_APIC 1
819 struct multiple_apic_table
821 ACPI_TABLE_HEADER_DEF /* ACPI common table header */
822 u32 local_apic_address; /* Physical address of local APIC */
824 u32 PCATcompat : 1; /* A one indicates system also has dual 8259s */
832 /* Values for Type in APIC_HEADER_DEF */
834 #define APIC_PROCESSOR 0
836 #define APIC_XRUPT_OVERRIDE 2
838 #define APIC_LOCAL_NMI 4
839 #define APIC_ADDRESS_OVERRIDE 5
840 #define APIC_IO_SAPIC 6
841 #define APIC_LOCAL_SAPIC 7
842 #define APIC_XRUPT_SOURCE 8
843 #define APIC_RESERVED 9 /* 9 and greater are reserved */
846 * MADT sub-structures (Follow MULTIPLE_APIC_DESCRIPTION_TABLE)
848 #define APIC_HEADER_DEF /* Common APIC sub-structure header */\
852 /* Sub-structures for MADT */
854 struct madt_processor_apic
857 u8 processor_id; /* ACPI processor id */
858 u8 local_apic_id; /* Processor's local APIC id */
860 u32 processor_enabled: 1; /* Processor is usable if set */
861 u32 reserved2 : 31; /* Reserved, must be zero */
870 u8 io_apic_id; /* I/O APIC ID */
871 u8 reserved; /* Reserved - must be zero */
872 u32 address; /* APIC physical address */
873 u32 interrupt; /* Global system interrupt where INTI
877 #include "acpi-dsdt.hex"
879 static inline u16 cpu_to_le16(u16 x)
884 static inline u32 cpu_to_le32(u32 x)
889 static void acpi_build_table_header(struct acpi_table_header *h,
890 char *sig, int len, u8 rev)
892 memcpy(h->signature, sig, 4);
893 h->length = cpu_to_le32(len);
895 #if (CONFIG_QEMU == 1)
896 memcpy(h->oem_id, "QEMU ", 6);
897 memcpy(h->oem_table_id, "QEMU", 4);
899 memcpy(h->oem_id, "BOCHS ", 6);
900 memcpy(h->oem_table_id, "BXPC", 4);
902 memcpy(h->oem_table_id + 4, sig, 4);
903 h->oem_revision = cpu_to_le32(1);
904 #if (CONFIG_QEMU == 1)
905 memcpy(h->asl_compiler_id, "QEMU", 4);
907 memcpy(h->asl_compiler_id, "BXPC", 4);
909 h->asl_compiler_revision = cpu_to_le32(1);
910 h->checksum = -checksum((void *)h, len);
913 int acpi_build_processor_ssdt(u8 *ssdt)
917 int acpi_cpus = smp_cpus > 0xff ? 0xff : smp_cpus;
919 ssdt_ptr[9] = 0; // checksum;
920 ssdt_ptr += sizeof(struct acpi_table_header);
922 // caluculate the length of processor block and scope block excluding PkgLength
923 length = 0x0d * acpi_cpus + 4;
925 // build processor scope header
926 *(ssdt_ptr++) = 0x10; // ScopeOp
927 if (length <= 0x3e) {
928 *(ssdt_ptr++) = length + 1;
930 *(ssdt_ptr++) = 0x7F;
931 *(ssdt_ptr++) = (length + 2) >> 6;
933 *(ssdt_ptr++) = '_'; // Name
938 // build object for each processor
939 for(i=0;i<acpi_cpus;i++) {
940 *(ssdt_ptr++) = 0x5B; // ProcessorOp
941 *(ssdt_ptr++) = 0x83;
942 *(ssdt_ptr++) = 0x0B; // Length
943 *(ssdt_ptr++) = 'C'; // Name (CPUxx)
946 *(ssdt_ptr++) = (i >> 4) < 0xa ? (i >> 4) + '0' : (i >> 4) + 'A' - 0xa;
949 *(ssdt_ptr++) = (i & 0xf) < 0xa ? (i & 0xf) + '0' : (i & 0xf) + 'A' - 0xa;
951 *(ssdt_ptr++) = 0x10; // Processor block address
952 *(ssdt_ptr++) = 0xb0;
955 *(ssdt_ptr++) = 6; // Processor block length
958 acpi_build_table_header((struct acpi_table_header *)ssdt,
959 "SSDT", ssdt_ptr - ssdt, 1);
961 return ssdt_ptr - ssdt;
964 /* base_addr must be a multiple of 4KB */
965 void acpi_bios_init(void)
967 struct rsdp_descriptor *rsdp;
968 struct rsdt_descriptor_rev1 *rsdt;
969 struct fadt_descriptor_rev1 *fadt;
970 struct facs_descriptor_rev1 *facs;
971 struct multiple_apic_table *madt;
973 u32 base_addr, rsdt_addr, fadt_addr, addr, facs_addr, dsdt_addr, ssdt_addr;
974 u32 acpi_tables_size, madt_addr, madt_size;
977 /* reserve memory space for tables */
978 #if (CONFIG_USE_EBDA_TABLES == 1)
979 ebda_cur_addr = align(ebda_cur_addr, 16);
980 rsdp = (void *)(ebda_cur_addr);
981 ebda_cur_addr += sizeof(*rsdp);
983 bios_table_cur_addr = align(bios_table_cur_addr, 16);
984 rsdp = (void *)(bios_table_cur_addr);
985 bios_table_cur_addr += sizeof(*rsdp);
988 addr = base_addr = GET_EBDA(ram_size) - CONFIG_ACPI_DATA_SIZE;
990 rsdt = (void *)(addr);
991 addr += sizeof(*rsdt);
994 fadt = (void *)(addr);
995 addr += sizeof(*fadt);
997 /* XXX: FACS should be in RAM */
998 addr = (addr + 63) & ~63; /* 64 byte alignment for FACS */
1000 facs = (void *)(addr);
1001 addr += sizeof(*facs);
1004 dsdt = (void *)(addr);
1005 addr += sizeof(AmlCode);
1008 ssdt = (void *)(addr);
1009 addr += acpi_build_processor_ssdt(ssdt);
1011 addr = (addr + 7) & ~7;
1013 madt_size = sizeof(*madt) +
1014 sizeof(struct madt_processor_apic) * smp_cpus +
1015 sizeof(struct madt_io_apic);
1016 madt = (void *)(addr);
1019 acpi_tables_size = addr - base_addr;
1021 dprintf(1, "ACPI tables: RSDP addr=0x%08lx"
1022 " ACPI DATA addr=0x%08lx size=0x%x\n",
1023 (unsigned long)rsdp,
1024 (unsigned long)rsdt, acpi_tables_size);
1027 memset(rsdp, 0, sizeof(*rsdp));
1028 memcpy(rsdp->signature, "RSD PTR ", 8);
1029 #if (CONFIG_QEMU == 1)
1030 memcpy(rsdp->oem_id, "QEMU ", 6);
1032 memcpy(rsdp->oem_id, "BOCHS ", 6);
1034 rsdp->rsdt_physical_address = cpu_to_le32(rsdt_addr);
1035 rsdp->checksum = -checksum((void *)rsdp, 20);
1038 memset(rsdt, 0, sizeof(*rsdt));
1039 rsdt->table_offset_entry[0] = cpu_to_le32(fadt_addr);
1040 rsdt->table_offset_entry[1] = cpu_to_le32(madt_addr);
1041 rsdt->table_offset_entry[2] = cpu_to_le32(ssdt_addr);
1042 acpi_build_table_header((struct acpi_table_header *)rsdt,
1043 "RSDT", sizeof(*rsdt), 1);
1046 memset(fadt, 0, sizeof(*fadt));
1047 fadt->firmware_ctrl = cpu_to_le32(facs_addr);
1048 fadt->dsdt = cpu_to_le32(dsdt_addr);
1050 fadt->reserved1 = 0;
1051 fadt->sci_int = cpu_to_le16(pm_sci_int);
1052 fadt->smi_cmd = cpu_to_le32(SMI_CMD_IO_ADDR);
1053 fadt->acpi_enable = 0xf1;
1054 fadt->acpi_disable = 0xf0;
1055 fadt->pm1a_evt_blk = cpu_to_le32(pm_io_base);
1056 fadt->pm1a_cnt_blk = cpu_to_le32(pm_io_base + 0x04);
1057 fadt->pm_tmr_blk = cpu_to_le32(pm_io_base + 0x08);
1058 fadt->pm1_evt_len = 4;
1059 fadt->pm1_cnt_len = 2;
1060 fadt->pm_tmr_len = 4;
1061 fadt->plvl2_lat = cpu_to_le16(0xfff); // C2 state not supported
1062 fadt->plvl3_lat = cpu_to_le16(0xfff); // C3 state not supported
1063 /* WBINVD + PROC_C1 + PWR_BUTTON + SLP_BUTTON + FIX_RTC */
1064 fadt->flags = cpu_to_le32((1 << 0) | (1 << 2) | (1 << 4) | (1 << 5) | (1 << 6));
1065 acpi_build_table_header((struct acpi_table_header *)fadt, "FACP",
1069 memset(facs, 0, sizeof(*facs));
1070 memcpy(facs->signature, "FACS", 4);
1071 facs->length = cpu_to_le32(sizeof(*facs));
1074 memcpy(dsdt, AmlCode, sizeof(AmlCode));
1078 struct madt_processor_apic *apic;
1079 struct madt_io_apic *io_apic;
1081 memset(madt, 0, madt_size);
1082 madt->local_apic_address = cpu_to_le32(0xfee00000);
1083 madt->flags = cpu_to_le32(1);
1084 apic = (void *)(madt + 1);
1085 for(i=0;i<smp_cpus;i++) {
1086 apic->type = APIC_PROCESSOR;
1087 apic->length = sizeof(*apic);
1088 apic->processor_id = i;
1089 apic->local_apic_id = i;
1090 apic->flags = cpu_to_le32(1);
1093 io_apic = (void *)apic;
1094 io_apic->type = APIC_IO;
1095 io_apic->length = sizeof(*io_apic);
1096 io_apic->io_apic_id = smp_cpus;
1097 io_apic->address = cpu_to_le32(0xfec00000);
1098 io_apic->interrupt = cpu_to_le32(0);
1100 acpi_build_table_header((struct acpi_table_header *)madt,
1101 "APIC", madt_size, 1);
1105 /* SMBIOS entry point -- must be written to a 16-bit aligned address
1106 between 0xf0000 and 0xfffff.
1108 struct smbios_entry_point {
1109 char anchor_string[4];
1112 u8 smbios_major_version;
1113 u8 smbios_minor_version;
1114 u16 max_structure_size;
1115 u8 entry_point_revision;
1116 u8 formatted_area[5];
1117 char intermediate_anchor_string[5];
1118 u8 intermediate_checksum;
1119 u16 structure_table_length;
1120 u32 structure_table_address;
1121 u16 number_of_structures;
1122 u8 smbios_bcd_revision;
1123 } __attribute__((__packed__));
1125 /* This goes at the beginning of every SMBIOS structure. */
1126 struct smbios_structure_header {
1130 } __attribute__((__packed__));
1132 /* SMBIOS type 0 - BIOS Information */
1133 struct smbios_type_0 {
1134 struct smbios_structure_header header;
1136 u8 bios_version_str;
1137 u16 bios_starting_address_segment;
1138 u8 bios_release_date_str;
1140 u8 bios_characteristics[8];
1141 u8 bios_characteristics_extension_bytes[2];
1142 u8 system_bios_major_release;
1143 u8 system_bios_minor_release;
1144 u8 embedded_controller_major_release;
1145 u8 embedded_controller_minor_release;
1146 } __attribute__((__packed__));
1148 /* SMBIOS type 1 - System Information */
1149 struct smbios_type_1 {
1150 struct smbios_structure_header header;
1151 u8 manufacturer_str;
1152 u8 product_name_str;
1154 u8 serial_number_str;
1159 } __attribute__((__packed__));
1161 /* SMBIOS type 3 - System Enclosure (v2.3) */
1162 struct smbios_type_3 {
1163 struct smbios_structure_header header;
1164 u8 manufacturer_str;
1167 u8 serial_number_str;
1168 u8 asset_tag_number_str;
1170 u8 power_supply_state;
1175 u8 number_of_power_cords;
1176 u8 contained_element_count;
1177 // contained elements follow
1178 } __attribute__((__packed__));
1180 /* SMBIOS type 4 - Processor Information (v2.0) */
1181 struct smbios_type_4 {
1182 struct smbios_structure_header header;
1183 u8 socket_designation_str;
1185 u8 processor_family;
1186 u8 processor_manufacturer_str;
1187 u32 processor_id[2];
1188 u8 processor_version_str;
1194 u8 processor_upgrade;
1195 } __attribute__((__packed__));
1197 /* SMBIOS type 16 - Physical Memory Array
1198 * Associated with one type 17 (Memory Device).
1200 struct smbios_type_16 {
1201 struct smbios_structure_header header;
1204 u8 error_correction;
1205 u32 maximum_capacity;
1206 u16 memory_error_information_handle;
1207 u16 number_of_memory_devices;
1208 } __attribute__((__packed__));
1210 /* SMBIOS type 17 - Memory Device
1211 * Associated with one type 19
1213 struct smbios_type_17 {
1214 struct smbios_structure_header header;
1215 u16 physical_memory_array_handle;
1216 u16 memory_error_information_handle;
1222 u8 device_locator_str;
1223 u8 bank_locator_str;
1226 } __attribute__((__packed__));
1228 /* SMBIOS type 19 - Memory Array Mapped Address */
1229 struct smbios_type_19 {
1230 struct smbios_structure_header header;
1231 u32 starting_address;
1233 u16 memory_array_handle;
1235 } __attribute__((__packed__));
1237 /* SMBIOS type 20 - Memory Device Mapped Address */
1238 struct smbios_type_20 {
1239 struct smbios_structure_header header;
1240 u32 starting_address;
1242 u16 memory_device_handle;
1243 u16 memory_array_mapped_address_handle;
1244 u8 partition_row_position;
1245 u8 interleave_position;
1246 u8 interleaved_data_depth;
1247 } __attribute__((__packed__));
1249 /* SMBIOS type 32 - System Boot Information */
1250 struct smbios_type_32 {
1251 struct smbios_structure_header header;
1254 } __attribute__((__packed__));
1256 /* SMBIOS type 127 -- End-of-table */
1257 struct smbios_type_127 {
1258 struct smbios_structure_header header;
1259 } __attribute__((__packed__));
1262 smbios_entry_point_init(void *start,
1263 u16 max_structure_size,
1264 u16 structure_table_length,
1265 u32 structure_table_address,
1266 u16 number_of_structures)
1268 struct smbios_entry_point *ep = (struct smbios_entry_point *)start;
1270 memcpy(ep->anchor_string, "_SM_", 4);
1272 ep->smbios_major_version = 2;
1273 ep->smbios_minor_version = 4;
1274 ep->max_structure_size = max_structure_size;
1275 ep->entry_point_revision = 0;
1276 memset(ep->formatted_area, 0, 5);
1277 memcpy(ep->intermediate_anchor_string, "_DMI_", 5);
1279 ep->structure_table_length = structure_table_length;
1280 ep->structure_table_address = structure_table_address;
1281 ep->number_of_structures = number_of_structures;
1282 ep->smbios_bcd_revision = 0x24;
1285 ep->intermediate_checksum = 0;
1287 ep->checksum = -checksum(start, 0x10);
1289 ep->intermediate_checksum = -checksum(start + 0x10, ep->length - 0x10);
1292 /* Type 0 -- BIOS Information */
1293 #define RELEASE_DATE_STR "01/01/2007"
1295 smbios_type_0_init(void *start)
1297 struct smbios_type_0 *p = (struct smbios_type_0 *)start;
1300 p->header.length = sizeof(struct smbios_type_0);
1301 p->header.handle = 0;
1304 p->bios_version_str = 1;
1305 p->bios_starting_address_segment = 0xe800;
1306 p->bios_release_date_str = 2;
1307 p->bios_rom_size = 0; /* FIXME */
1309 memset(p->bios_characteristics, 0, 7);
1310 p->bios_characteristics[7] = 0x08; /* BIOS characteristics not supported */
1311 p->bios_characteristics_extension_bytes[0] = 0;
1312 p->bios_characteristics_extension_bytes[1] = 0;
1314 p->system_bios_major_release = 1;
1315 p->system_bios_minor_release = 0;
1316 p->embedded_controller_major_release = 0xff;
1317 p->embedded_controller_minor_release = 0xff;
1319 start += sizeof(struct smbios_type_0);
1320 memcpy((char *)start, CONFIG_APPNAME, sizeof(CONFIG_APPNAME));
1321 start += sizeof(CONFIG_APPNAME);
1322 memcpy((char *)start, RELEASE_DATE_STR, sizeof(RELEASE_DATE_STR));
1323 start += sizeof(RELEASE_DATE_STR);
1329 /* Type 1 -- System Information */
1331 smbios_type_1_init(void *start)
1333 struct smbios_type_1 *p = (struct smbios_type_1 *)start;
1335 p->header.length = sizeof(struct smbios_type_1);
1336 p->header.handle = 0x100;
1338 p->manufacturer_str = 0;
1339 p->product_name_str = 0;
1341 p->serial_number_str = 0;
1343 memcpy(p->uuid, bios_uuid, 16);
1345 p->wake_up_type = 0x06; /* power switch */
1346 p->sku_number_str = 0;
1349 start += sizeof(struct smbios_type_1);
1350 *((u16 *)start) = 0;
1355 /* Type 3 -- System Enclosure */
1357 smbios_type_3_init(void *start)
1359 struct smbios_type_3 *p = (struct smbios_type_3 *)start;
1362 p->header.length = sizeof(struct smbios_type_3);
1363 p->header.handle = 0x300;
1365 p->manufacturer_str = 0;
1366 p->type = 0x01; /* other */
1368 p->serial_number_str = 0;
1369 p->asset_tag_number_str = 0;
1370 p->boot_up_state = 0x03; /* safe */
1371 p->power_supply_state = 0x03; /* safe */
1372 p->thermal_state = 0x03; /* safe */
1373 p->security_status = 0x02; /* unknown */
1376 p->number_of_power_cords = 0;
1377 p->contained_element_count = 0;
1379 start += sizeof(struct smbios_type_3);
1380 *((u16 *)start) = 0;
1385 /* Type 4 -- Processor Information */
1387 smbios_type_4_init(void *start, unsigned int cpu_number)
1389 struct smbios_type_4 *p = (struct smbios_type_4 *)start;
1392 p->header.length = sizeof(struct smbios_type_4);
1393 p->header.handle = 0x400 + cpu_number;
1395 p->socket_designation_str = 1;
1396 p->processor_type = 0x03; /* CPU */
1397 p->processor_family = 0x01; /* other */
1398 p->processor_manufacturer_str = 0;
1400 p->processor_id[0] = cpuid_signature;
1401 p->processor_id[1] = cpuid_features;
1403 p->processor_version_str = 0;
1405 p->external_clock = 0;
1407 p->max_speed = 0; /* unknown */
1408 p->current_speed = 0; /* unknown */
1410 p->status = 0x41; /* socket populated, CPU enabled */
1411 p->processor_upgrade = 0x01; /* other */
1413 start += sizeof(struct smbios_type_4);
1415 memcpy((char *)start, "CPU " "\0" "" "\0" "", 7);
1416 ((char *)start)[4] = cpu_number + '0';
1421 /* Type 16 -- Physical Memory Array */
1423 smbios_type_16_init(void *start, u32 memsize)
1425 struct smbios_type_16 *p = (struct smbios_type_16*)start;
1427 p->header.type = 16;
1428 p->header.length = sizeof(struct smbios_type_16);
1429 p->header.handle = 0x1000;
1431 p->location = 0x01; /* other */
1432 p->use = 0x03; /* system memory */
1433 p->error_correction = 0x01; /* other */
1434 p->maximum_capacity = memsize * 1024;
1435 p->memory_error_information_handle = 0xfffe; /* none provided */
1436 p->number_of_memory_devices = 1;
1438 start += sizeof(struct smbios_type_16);
1439 *((u16 *)start) = 0;
1444 /* Type 17 -- Memory Device */
1446 smbios_type_17_init(void *start, u32 memory_size_mb)
1448 struct smbios_type_17 *p = (struct smbios_type_17 *)start;
1450 p->header.type = 17;
1451 p->header.length = sizeof(struct smbios_type_17);
1452 p->header.handle = 0x1100;
1454 p->physical_memory_array_handle = 0x1000;
1455 p->total_width = 64;
1457 /* truncate memory_size_mb to 16 bits and clear most significant
1458 bit [indicates size in MB] */
1459 p->size = (u16) memory_size_mb & 0x7fff;
1460 p->form_factor = 0x09; /* DIMM */
1462 p->device_locator_str = 1;
1463 p->bank_locator_str = 0;
1464 p->memory_type = 0x07; /* RAM */
1467 start += sizeof(struct smbios_type_17);
1468 memcpy((char *)start, "DIMM 1", 7);
1475 /* Type 19 -- Memory Array Mapped Address */
1477 smbios_type_19_init(void *start, u32 memory_size_mb)
1479 struct smbios_type_19 *p = (struct smbios_type_19 *)start;
1481 p->header.type = 19;
1482 p->header.length = sizeof(struct smbios_type_19);
1483 p->header.handle = 0x1300;
1485 p->starting_address = 0;
1486 p->ending_address = (memory_size_mb-1) * 1024;
1487 p->memory_array_handle = 0x1000;
1488 p->partition_width = 1;
1490 start += sizeof(struct smbios_type_19);
1491 *((u16 *)start) = 0;
1496 /* Type 20 -- Memory Device Mapped Address */
1498 smbios_type_20_init(void *start, u32 memory_size_mb)
1500 struct smbios_type_20 *p = (struct smbios_type_20 *)start;
1502 p->header.type = 20;
1503 p->header.length = sizeof(struct smbios_type_20);
1504 p->header.handle = 0x1400;
1506 p->starting_address = 0;
1507 p->ending_address = (memory_size_mb-1)*1024;
1508 p->memory_device_handle = 0x1100;
1509 p->memory_array_mapped_address_handle = 0x1300;
1510 p->partition_row_position = 1;
1511 p->interleave_position = 0;
1512 p->interleaved_data_depth = 0;
1514 start += sizeof(struct smbios_type_20);
1516 *((u16 *)start) = 0;
1520 /* Type 32 -- System Boot Information */
1522 smbios_type_32_init(void *start)
1524 struct smbios_type_32 *p = (struct smbios_type_32 *)start;
1526 p->header.type = 32;
1527 p->header.length = sizeof(struct smbios_type_32);
1528 p->header.handle = 0x2000;
1529 memset(p->reserved, 0, 6);
1530 p->boot_status = 0; /* no errors detected */
1532 start += sizeof(struct smbios_type_32);
1533 *((u16 *)start) = 0;
1538 /* Type 127 -- End of Table */
1540 smbios_type_127_init(void *start)
1542 struct smbios_type_127 *p = (struct smbios_type_127 *)start;
1544 p->header.type = 127;
1545 p->header.length = sizeof(struct smbios_type_127);
1546 p->header.handle = 0x7f00;
1548 start += sizeof(struct smbios_type_127);
1549 *((u16 *)start) = 0;
1554 void smbios_init(void)
1556 unsigned cpu_num, nr_structs = 0, max_struct_size = 0;
1557 char *start, *p, *q;
1558 int memsize = GET_EBDA(ram_size) / (1024 * 1024);
1560 #if (CONFIG_USE_EBDA_TABLES == 1)
1561 ebda_cur_addr = align(ebda_cur_addr, 16);
1562 start = (void *)(ebda_cur_addr);
1564 bios_table_cur_addr = align(bios_table_cur_addr, 16);
1565 start = (void *)(bios_table_cur_addr);
1568 p = (char *)start + sizeof(struct smbios_entry_point);
1570 #define add_struct(fn) { \
1573 if ((q - p) > max_struct_size) \
1574 max_struct_size = q - p; \
1578 add_struct(smbios_type_0_init(p));
1579 add_struct(smbios_type_1_init(p));
1580 add_struct(smbios_type_3_init(p));
1581 for (cpu_num = 1; cpu_num <= smp_cpus; cpu_num++)
1582 add_struct(smbios_type_4_init(p, cpu_num));
1583 add_struct(smbios_type_16_init(p, memsize));
1584 add_struct(smbios_type_17_init(p, memsize));
1585 add_struct(smbios_type_19_init(p, memsize));
1586 add_struct(smbios_type_20_init(p, memsize));
1587 add_struct(smbios_type_32_init(p));
1588 add_struct(smbios_type_127_init(p));
1592 smbios_entry_point_init(
1593 start, max_struct_size,
1594 (p - (char *)start) - sizeof(struct smbios_entry_point),
1595 (u32)(start + sizeof(struct smbios_entry_point)),
1598 #if (CONFIG_USE_EBDA_TABLES == 1)
1599 ebda_cur_addr += (p - (char *)start);
1601 bios_table_cur_addr += (p - (char *)start);
1604 dprintf(1, "SMBIOS table addr=0x%08lx\n", (unsigned long)start);
1607 void rombios32_init(void)
1609 if (CONFIG_COREBOOT)
1610 // XXX - not supported on coreboot yet.
1613 dprintf(1, "Starting rombios32\n");
1615 #if (CONFIG_USE_EBDA_TABLES == 1)
1616 ebda_cur_addr = ((*(u16 *)(0x40e)) << 4) + 0x380;
1617 dprintf(1, "ebda_cur_addr: 0x%08lx\n", ebda_cur_addr);
1620 bios_table_cur_addr = 0xf0000 | OFFSET_freespace2_start;
1621 bios_table_end_addr = 0xf0000 | OFFSET_freespace2_end;
1622 dprintf(1, "bios_table_addr: 0x%08lx end=0x%08lx\n",
1623 bios_table_cur_addr, bios_table_end_addr);
1631 if (bios_table_cur_addr != 0) {
1642 dprintf(1, "bios_table_cur_addr: 0x%08lx\n", bios_table_cur_addr);
1643 if (bios_table_cur_addr > bios_table_end_addr)
1644 BX_PANIC("bios_table_end_addr overflow!\n");