1 /////////////////////////////////////////////////////////////////////////
3 // 32 bit Bochs BIOS init code
4 // Copyright (C) 2006 Fabrice Bellard
6 // This library is free software; you can redistribute it and/or
7 // modify it under the terms of the GNU Lesser General Public
8 // License as published by the Free Software Foundation; either
9 // version 2 of the License, or (at your option) any later version.
11 // This library is distributed in the hope that it will be useful,
12 // but WITHOUT ANY WARRANTY; without even the implied warranty of
13 // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 // Lesser General Public License for more details.
16 // You should have received a copy of the GNU Lesser General Public
17 // License along with this library; if not, write to the Free Software
18 // Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
20 #include "util.h" // dprintf
21 #include "pci.h" // PCIDevice
22 #include "types.h" // u32
23 #include "config.h" // CONFIG_*
24 #include "memmap.h" // bios_table_cur_addr
25 #include "acpi.h" // acpi_bios_init
29 u32 cpuid_ext_features;
34 // Default to UUID not set
35 memset(bios_uuid, 0, 16);
40 // check if backdoor port exists
41 u32 eax, ebx, ecx, edx;
42 asm volatile ("outl %%eax, %%dx"
43 : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx)
44 : "a" (0x564d5868), "c" (0xa), "d" (0x5658));
45 if (ebx != 0x564d5868)
48 u32 *uuid_ptr = (u32 *)bios_uuid;
50 asm volatile ("outl %%eax, %%dx"
51 : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx)
52 : "a" (0x564d5868), "c" (0x13), "d" (0x5658));
61 u32 eax, ebx, ecx, edx;
62 cpuid(1, &eax, &ebx, &ecx, &edx);
63 cpuid_signature = eax;
65 cpuid_ext_features = ecx;
68 /****************************************************/
71 #define PCI_ADDRESS_SPACE_MEM 0x00
72 #define PCI_ADDRESS_SPACE_IO 0x01
73 #define PCI_ADDRESS_SPACE_MEM_PREFETCH 0x08
75 #define PCI_ROM_SLOT 6
76 #define PCI_NUM_REGIONS 7
78 #define PCI_DEVICES_MAX 64
80 static u32 pci_bios_io_addr;
81 static u32 pci_bios_mem_addr;
82 static u32 pci_bios_bigmem_addr;
83 /* host irqs corresponding to PCI irqs A-D */
84 static u8 pci_irqs[4] = { 11, 9, 11, 9 };
86 static void pci_set_io_region_addr(PCIDevice d, int region_num, u32 addr)
91 if ( region_num == PCI_ROM_SLOT ) {
94 ofs = 0x10 + region_num * 4;
97 old_addr = pci_config_readl(d, ofs);
99 pci_config_writel(d, ofs, addr);
100 dprintf(1, "region %d: 0x%08x\n", region_num, addr);
102 /* enable memory mappings */
103 cmd = pci_config_readw(d, PCI_COMMAND);
104 if ( region_num == PCI_ROM_SLOT )
106 else if (old_addr & PCI_ADDRESS_SPACE_IO)
110 pci_config_writew(d, PCI_COMMAND, cmd);
113 /* return the global irq number corresponding to a given device irq
114 pin. We could also use the bus number to have a more precise
116 static int pci_slot_get_pirq(PCIDevice pci_dev, int irq_num)
119 slot_addend = (pci_dev.devfn >> 3) - 1;
120 return (irq_num + slot_addend) & 3;
123 static void pci_bios_init_bridges(PCIDevice d)
125 u16 vendor_id, device_id;
127 vendor_id = pci_config_readw(d, PCI_VENDOR_ID);
128 device_id = pci_config_readw(d, PCI_DEVICE_ID);
130 if (vendor_id == 0x8086 && device_id == 0x7000) {
138 for(i = 0; i < 4; i++) {
140 /* set to trigger level */
141 elcr[irq >> 3] |= (1 << (irq & 7));
142 /* activate irq remapping in PIIX */
143 pci_config_writeb(d, 0x60 + i, irq);
145 outb(elcr[0], 0x4d0);
146 outb(elcr[1], 0x4d1);
147 dprintf(1, "PIIX3 init: elcr=%02x %02x\n",
152 static void pci_bios_init_device(PCIDevice d)
156 int i, pin, pic_irq, vendor_id, device_id;
158 class = pci_config_readw(d, PCI_CLASS_DEVICE);
159 vendor_id = pci_config_readw(d, PCI_VENDOR_ID);
160 device_id = pci_config_readw(d, PCI_DEVICE_ID);
161 dprintf(1, "PCI: bus=%d devfn=0x%02x: vendor_id=0x%04x device_id=0x%04x\n",
162 d.bus, d.devfn, vendor_id, device_id);
165 if (vendor_id == 0x8086 && device_id == 0x7010) {
167 pci_config_writew(d, 0x40, 0x8000); // enable IDE0
168 pci_config_writew(d, 0x42, 0x8000); // enable IDE1
171 /* IDE: we map it as in ISA mode */
172 pci_set_io_region_addr(d, 0, 0x1f0);
173 pci_set_io_region_addr(d, 1, 0x3f4);
174 pci_set_io_region_addr(d, 2, 0x170);
175 pci_set_io_region_addr(d, 3, 0x374);
179 if (vendor_id != 0x1234)
181 /* VGA: map frame buffer to default Bochs VBE address */
182 pci_set_io_region_addr(d, 0, 0xE0000000);
186 if (vendor_id == 0x1014) {
188 if (device_id == 0x0046 || device_id == 0xFFFF) {
190 pci_set_io_region_addr(d, 0, 0x80800000 + 0x00040000);
195 if (vendor_id == 0x0106b &&
196 (device_id == 0x0017 || device_id == 0x0022)) {
198 pci_set_io_region_addr(d, 0, 0x80800000);
203 /* default memory mappings */
204 for(i = 0; i < PCI_NUM_REGIONS; i++) {
208 if (i == PCI_ROM_SLOT)
212 pci_config_writel(d, ofs, 0xffffffff);
213 val = pci_config_readl(d, ofs);
215 size = (~(val & ~0xf)) + 1;
216 if (val & PCI_ADDRESS_SPACE_IO)
217 paddr = &pci_bios_io_addr;
218 else if (size >= 0x04000000)
219 paddr = &pci_bios_bigmem_addr;
221 paddr = &pci_bios_mem_addr;
222 *paddr = (*paddr + size - 1) & ~(size - 1);
223 pci_set_io_region_addr(d, i, *paddr);
230 /* map the interrupt */
231 pin = pci_config_readb(d, PCI_INTERRUPT_PIN);
233 pin = pci_slot_get_pirq(d, pin - 1);
234 pic_irq = pci_irqs[pin];
235 pci_config_writeb(d, PCI_INTERRUPT_LINE, pic_irq);
238 if (vendor_id == 0x8086 && device_id == 0x7113) {
239 /* PIIX4 Power Management device (for ACPI) */
240 u32 pm_io_base = BUILD_PM_IO_BASE;
241 pci_config_writel(d, 0x40, pm_io_base | 1);
242 pci_config_writeb(d, 0x80, 0x01); /* enable PM io space */
243 u32 smb_io_base = BUILD_SMB_IO_BASE;
244 pci_config_writel(d, 0x90, smb_io_base | 1);
245 pci_config_writeb(d, 0xd2, 0x09); /* enable SMBus io space */
249 void pci_for_each_device(void (*init_func)(PCIDevice d))
252 u16 vendor_id, device_id;
254 for(bus = 0; bus < 1; bus++) {
255 for(devfn = 0; devfn < 256; devfn++) {
256 PCIDevice d = pci_bd(bus, devfn);
257 vendor_id = pci_config_readw(d, PCI_VENDOR_ID);
258 device_id = pci_config_readw(d, PCI_DEVICE_ID);
259 if (vendor_id != 0xffff || device_id != 0xffff) {
266 void pci_bios_init(void)
268 pci_bios_io_addr = 0xc000;
269 pci_bios_mem_addr = 0xf0000000;
270 pci_bios_bigmem_addr = GET_EBDA(ram_size);
271 if (pci_bios_bigmem_addr < 0x90000000)
272 pci_bios_bigmem_addr = 0x90000000;
274 pci_for_each_device(pci_bios_init_bridges);
276 pci_for_each_device(pci_bios_init_device);
279 /* SMBIOS entry point -- must be written to a 16-bit aligned address
280 between 0xf0000 and 0xfffff.
282 struct smbios_entry_point {
283 char anchor_string[4];
286 u8 smbios_major_version;
287 u8 smbios_minor_version;
288 u16 max_structure_size;
289 u8 entry_point_revision;
290 u8 formatted_area[5];
291 char intermediate_anchor_string[5];
292 u8 intermediate_checksum;
293 u16 structure_table_length;
294 u32 structure_table_address;
295 u16 number_of_structures;
296 u8 smbios_bcd_revision;
297 } __attribute__((__packed__));
299 /* This goes at the beginning of every SMBIOS structure. */
300 struct smbios_structure_header {
304 } __attribute__((__packed__));
306 /* SMBIOS type 0 - BIOS Information */
307 struct smbios_type_0 {
308 struct smbios_structure_header header;
311 u16 bios_starting_address_segment;
312 u8 bios_release_date_str;
314 u8 bios_characteristics[8];
315 u8 bios_characteristics_extension_bytes[2];
316 u8 system_bios_major_release;
317 u8 system_bios_minor_release;
318 u8 embedded_controller_major_release;
319 u8 embedded_controller_minor_release;
320 } __attribute__((__packed__));
322 /* SMBIOS type 1 - System Information */
323 struct smbios_type_1 {
324 struct smbios_structure_header header;
328 u8 serial_number_str;
333 } __attribute__((__packed__));
335 /* SMBIOS type 3 - System Enclosure (v2.3) */
336 struct smbios_type_3 {
337 struct smbios_structure_header header;
341 u8 serial_number_str;
342 u8 asset_tag_number_str;
344 u8 power_supply_state;
349 u8 number_of_power_cords;
350 u8 contained_element_count;
351 // contained elements follow
352 } __attribute__((__packed__));
354 /* SMBIOS type 4 - Processor Information (v2.0) */
355 struct smbios_type_4 {
356 struct smbios_structure_header header;
357 u8 socket_designation_str;
360 u8 processor_manufacturer_str;
362 u8 processor_version_str;
368 u8 processor_upgrade;
369 } __attribute__((__packed__));
371 /* SMBIOS type 16 - Physical Memory Array
372 * Associated with one type 17 (Memory Device).
374 struct smbios_type_16 {
375 struct smbios_structure_header header;
379 u32 maximum_capacity;
380 u16 memory_error_information_handle;
381 u16 number_of_memory_devices;
382 } __attribute__((__packed__));
384 /* SMBIOS type 17 - Memory Device
385 * Associated with one type 19
387 struct smbios_type_17 {
388 struct smbios_structure_header header;
389 u16 physical_memory_array_handle;
390 u16 memory_error_information_handle;
396 u8 device_locator_str;
400 } __attribute__((__packed__));
402 /* SMBIOS type 19 - Memory Array Mapped Address */
403 struct smbios_type_19 {
404 struct smbios_structure_header header;
405 u32 starting_address;
407 u16 memory_array_handle;
409 } __attribute__((__packed__));
411 /* SMBIOS type 20 - Memory Device Mapped Address */
412 struct smbios_type_20 {
413 struct smbios_structure_header header;
414 u32 starting_address;
416 u16 memory_device_handle;
417 u16 memory_array_mapped_address_handle;
418 u8 partition_row_position;
419 u8 interleave_position;
420 u8 interleaved_data_depth;
421 } __attribute__((__packed__));
423 /* SMBIOS type 32 - System Boot Information */
424 struct smbios_type_32 {
425 struct smbios_structure_header header;
428 } __attribute__((__packed__));
430 /* SMBIOS type 127 -- End-of-table */
431 struct smbios_type_127 {
432 struct smbios_structure_header header;
433 } __attribute__((__packed__));
436 smbios_entry_point_init(void *start,
437 u16 max_structure_size,
438 u16 structure_table_length,
439 u32 structure_table_address,
440 u16 number_of_structures)
442 struct smbios_entry_point *ep = (struct smbios_entry_point *)start;
444 memcpy(ep->anchor_string, "_SM_", 4);
446 ep->smbios_major_version = 2;
447 ep->smbios_minor_version = 4;
448 ep->max_structure_size = max_structure_size;
449 ep->entry_point_revision = 0;
450 memset(ep->formatted_area, 0, 5);
451 memcpy(ep->intermediate_anchor_string, "_DMI_", 5);
453 ep->structure_table_length = structure_table_length;
454 ep->structure_table_address = structure_table_address;
455 ep->number_of_structures = number_of_structures;
456 ep->smbios_bcd_revision = 0x24;
459 ep->intermediate_checksum = 0;
461 ep->checksum = -checksum(start, 0x10);
463 ep->intermediate_checksum = -checksum(start + 0x10, ep->length - 0x10);
466 /* Type 0 -- BIOS Information */
467 #define RELEASE_DATE_STR "01/01/2007"
469 smbios_type_0_init(void *start)
471 struct smbios_type_0 *p = (struct smbios_type_0 *)start;
474 p->header.length = sizeof(struct smbios_type_0);
475 p->header.handle = 0;
478 p->bios_version_str = 1;
479 p->bios_starting_address_segment = 0xe800;
480 p->bios_release_date_str = 2;
481 p->bios_rom_size = 0; /* FIXME */
483 memset(p->bios_characteristics, 0, 7);
484 p->bios_characteristics[7] = 0x08; /* BIOS characteristics not supported */
485 p->bios_characteristics_extension_bytes[0] = 0;
486 p->bios_characteristics_extension_bytes[1] = 0;
488 p->system_bios_major_release = 1;
489 p->system_bios_minor_release = 0;
490 p->embedded_controller_major_release = 0xff;
491 p->embedded_controller_minor_release = 0xff;
493 start += sizeof(struct smbios_type_0);
494 memcpy((char *)start, CONFIG_APPNAME, sizeof(CONFIG_APPNAME));
495 start += sizeof(CONFIG_APPNAME);
496 memcpy((char *)start, RELEASE_DATE_STR, sizeof(RELEASE_DATE_STR));
497 start += sizeof(RELEASE_DATE_STR);
503 /* Type 1 -- System Information */
505 smbios_type_1_init(void *start)
507 struct smbios_type_1 *p = (struct smbios_type_1 *)start;
509 p->header.length = sizeof(struct smbios_type_1);
510 p->header.handle = 0x100;
512 p->manufacturer_str = 0;
513 p->product_name_str = 0;
515 p->serial_number_str = 0;
517 memcpy(p->uuid, bios_uuid, 16);
519 p->wake_up_type = 0x06; /* power switch */
520 p->sku_number_str = 0;
523 start += sizeof(struct smbios_type_1);
529 /* Type 3 -- System Enclosure */
531 smbios_type_3_init(void *start)
533 struct smbios_type_3 *p = (struct smbios_type_3 *)start;
536 p->header.length = sizeof(struct smbios_type_3);
537 p->header.handle = 0x300;
539 p->manufacturer_str = 0;
540 p->type = 0x01; /* other */
542 p->serial_number_str = 0;
543 p->asset_tag_number_str = 0;
544 p->boot_up_state = 0x03; /* safe */
545 p->power_supply_state = 0x03; /* safe */
546 p->thermal_state = 0x03; /* safe */
547 p->security_status = 0x02; /* unknown */
550 p->number_of_power_cords = 0;
551 p->contained_element_count = 0;
553 start += sizeof(struct smbios_type_3);
559 /* Type 4 -- Processor Information */
561 smbios_type_4_init(void *start, unsigned int cpu_number)
563 struct smbios_type_4 *p = (struct smbios_type_4 *)start;
566 p->header.length = sizeof(struct smbios_type_4);
567 p->header.handle = 0x400 + cpu_number;
569 p->socket_designation_str = 1;
570 p->processor_type = 0x03; /* CPU */
571 p->processor_family = 0x01; /* other */
572 p->processor_manufacturer_str = 0;
574 p->processor_id[0] = cpuid_signature;
575 p->processor_id[1] = cpuid_features;
577 p->processor_version_str = 0;
579 p->external_clock = 0;
581 p->max_speed = 0; /* unknown */
582 p->current_speed = 0; /* unknown */
584 p->status = 0x41; /* socket populated, CPU enabled */
585 p->processor_upgrade = 0x01; /* other */
587 start += sizeof(struct smbios_type_4);
589 memcpy((char *)start, "CPU " "\0" "" "\0" "", 7);
590 ((char *)start)[4] = cpu_number + '0';
595 /* Type 16 -- Physical Memory Array */
597 smbios_type_16_init(void *start, u32 memsize)
599 struct smbios_type_16 *p = (struct smbios_type_16*)start;
602 p->header.length = sizeof(struct smbios_type_16);
603 p->header.handle = 0x1000;
605 p->location = 0x01; /* other */
606 p->use = 0x03; /* system memory */
607 p->error_correction = 0x01; /* other */
608 p->maximum_capacity = memsize * 1024;
609 p->memory_error_information_handle = 0xfffe; /* none provided */
610 p->number_of_memory_devices = 1;
612 start += sizeof(struct smbios_type_16);
618 /* Type 17 -- Memory Device */
620 smbios_type_17_init(void *start, u32 memory_size_mb)
622 struct smbios_type_17 *p = (struct smbios_type_17 *)start;
625 p->header.length = sizeof(struct smbios_type_17);
626 p->header.handle = 0x1100;
628 p->physical_memory_array_handle = 0x1000;
631 /* truncate memory_size_mb to 16 bits and clear most significant
632 bit [indicates size in MB] */
633 p->size = (u16) memory_size_mb & 0x7fff;
634 p->form_factor = 0x09; /* DIMM */
636 p->device_locator_str = 1;
637 p->bank_locator_str = 0;
638 p->memory_type = 0x07; /* RAM */
641 start += sizeof(struct smbios_type_17);
642 memcpy((char *)start, "DIMM 1", 7);
649 /* Type 19 -- Memory Array Mapped Address */
651 smbios_type_19_init(void *start, u32 memory_size_mb)
653 struct smbios_type_19 *p = (struct smbios_type_19 *)start;
656 p->header.length = sizeof(struct smbios_type_19);
657 p->header.handle = 0x1300;
659 p->starting_address = 0;
660 p->ending_address = (memory_size_mb-1) * 1024;
661 p->memory_array_handle = 0x1000;
662 p->partition_width = 1;
664 start += sizeof(struct smbios_type_19);
670 /* Type 20 -- Memory Device Mapped Address */
672 smbios_type_20_init(void *start, u32 memory_size_mb)
674 struct smbios_type_20 *p = (struct smbios_type_20 *)start;
677 p->header.length = sizeof(struct smbios_type_20);
678 p->header.handle = 0x1400;
680 p->starting_address = 0;
681 p->ending_address = (memory_size_mb-1)*1024;
682 p->memory_device_handle = 0x1100;
683 p->memory_array_mapped_address_handle = 0x1300;
684 p->partition_row_position = 1;
685 p->interleave_position = 0;
686 p->interleaved_data_depth = 0;
688 start += sizeof(struct smbios_type_20);
694 /* Type 32 -- System Boot Information */
696 smbios_type_32_init(void *start)
698 struct smbios_type_32 *p = (struct smbios_type_32 *)start;
701 p->header.length = sizeof(struct smbios_type_32);
702 p->header.handle = 0x2000;
703 memset(p->reserved, 0, 6);
704 p->boot_status = 0; /* no errors detected */
706 start += sizeof(struct smbios_type_32);
712 /* Type 127 -- End of Table */
714 smbios_type_127_init(void *start)
716 struct smbios_type_127 *p = (struct smbios_type_127 *)start;
718 p->header.type = 127;
719 p->header.length = sizeof(struct smbios_type_127);
720 p->header.handle = 0x7f00;
722 start += sizeof(struct smbios_type_127);
728 void smbios_init(void)
730 unsigned cpu_num, nr_structs = 0, max_struct_size = 0;
732 int memsize = GET_EBDA(ram_size) / (1024 * 1024);
734 bios_table_cur_addr = ALIGN(bios_table_cur_addr, 16);
735 start = (void *)(bios_table_cur_addr);
737 p = (char *)start + sizeof(struct smbios_entry_point);
739 #define add_struct(fn) { \
742 if ((q - p) > max_struct_size) \
743 max_struct_size = q - p; \
747 add_struct(smbios_type_0_init(p));
748 add_struct(smbios_type_1_init(p));
749 add_struct(smbios_type_3_init(p));
750 int smp_cpus = smp_probe();
751 for (cpu_num = 1; cpu_num <= smp_cpus; cpu_num++)
752 add_struct(smbios_type_4_init(p, cpu_num));
753 add_struct(smbios_type_16_init(p, memsize));
754 add_struct(smbios_type_17_init(p, memsize));
755 add_struct(smbios_type_19_init(p, memsize));
756 add_struct(smbios_type_20_init(p, memsize));
757 add_struct(smbios_type_32_init(p));
758 add_struct(smbios_type_127_init(p));
762 smbios_entry_point_init(
763 start, max_struct_size,
764 (p - (char *)start) - sizeof(struct smbios_entry_point),
765 (u32)(start + sizeof(struct smbios_entry_point)),
768 bios_table_cur_addr += (p - (char *)start);
770 dprintf(1, "SMBIOS table addr=0x%08lx\n", (unsigned long)start);
773 void rombios32_init(void)
776 // XXX - not supported on coreboot yet.
779 dprintf(1, "Starting rombios32\n");
789 if (bios_table_cur_addr != 0) {
799 dprintf(1, "bios_table_cur_addr: 0x%08x\n", bios_table_cur_addr);
800 if (bios_table_cur_addr > bios_table_end_addr)
801 BX_PANIC("bios_table_end_addr overflow!\n");