1 // Initialize PCI devices (on emulators)
3 // Copyright (C) 2008 Kevin O'Connor <kevin@koconnor.net>
4 // Copyright (C) 2006 Fabrice Bellard
6 // This file may be distributed under the terms of the GNU LGPLv3 license.
8 #include "util.h" // dprintf
9 #include "pci.h" // pci_config_readl
10 #include "biosvar.h" // GET_EBDA
11 #include "pci_ids.h" // PCI_VENDOR_ID_INTEL
12 #include "pci_regs.h" // PCI_COMMAND
13 #include "xen.h" // usingXen
15 #define PCI_IO_INDEX_SHIFT 2
16 #define PCI_MEM_INDEX_SHIFT 12
18 #define PCI_BRIDGE_IO_MIN 0x1000
19 #define PCI_BRIDGE_MEM_MIN 0x100000
21 enum pci_region_type {
24 PCI_REGION_TYPE_PREFMEM,
25 PCI_REGION_TYPE_COUNT,
28 static const char *region_type_name[] = {
29 [ PCI_REGION_TYPE_IO ] = "io",
30 [ PCI_REGION_TYPE_MEM ] = "mem",
31 [ PCI_REGION_TYPE_PREFMEM ] = "prefmem",
36 /* pci region stats */
37 u32 count[32 - PCI_MEM_INDEX_SHIFT];
39 /* seconday bus region sizes */
41 /* pci region assignments */
42 u32 bases[32 - PCI_MEM_INDEX_SHIFT];
44 } r[PCI_REGION_TYPE_COUNT];
45 struct pci_device *bus_dev;
48 static int pci_size_to_index(u32 size, enum pci_region_type type)
50 int index = __fls(size);
51 int shift = (type == PCI_REGION_TYPE_IO) ?
52 PCI_IO_INDEX_SHIFT : PCI_MEM_INDEX_SHIFT;
60 static u32 pci_index_to_size(int index, enum pci_region_type type)
62 int shift = (type == PCI_REGION_TYPE_IO) ?
63 PCI_IO_INDEX_SHIFT : PCI_MEM_INDEX_SHIFT;
65 return 0x1 << (index + shift);
68 static enum pci_region_type pci_addr_to_type(u32 addr)
70 if (addr & PCI_BASE_ADDRESS_SPACE_IO)
71 return PCI_REGION_TYPE_IO;
72 if (addr & PCI_BASE_ADDRESS_MEM_PREFETCH)
73 return PCI_REGION_TYPE_PREFMEM;
74 return PCI_REGION_TYPE_MEM;
77 static u32 pci_bar(struct pci_device *pci, int region_num)
79 if (region_num != PCI_ROM_SLOT) {
80 return PCI_BASE_ADDRESS_0 + region_num * 4;
83 #define PCI_HEADER_TYPE_MULTI_FUNCTION 0x80
84 u8 type = pci->header_type & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
85 return type == PCI_HEADER_TYPE_BRIDGE ? PCI_ROM_ADDRESS1 : PCI_ROM_ADDRESS;
89 pci_set_io_region_addr(struct pci_device *pci, int region_num, u32 addr)
91 pci_config_writel(pci->bdf, pci_bar(pci, region_num), addr);
95 /****************************************************************
97 ****************************************************************/
99 /* host irqs corresponding to PCI irqs A-D */
100 const u8 pci_irqs[4] = {
104 // Return the global irq number corresponding to a host bus device irq pin.
105 static int pci_slot_get_irq(u16 bdf, int pin)
107 int slot_addend = pci_bdf_to_dev(bdf) - 1;
108 return pci_irqs[(pin - 1 + slot_addend) & 3];
111 /* PIIX3/PIIX4 PCI to ISA bridge */
112 static void piix_isa_bridge_init(struct pci_device *pci, void *arg)
119 for (i = 0; i < 4; i++) {
121 /* set to trigger level */
122 elcr[irq >> 3] |= (1 << (irq & 7));
123 /* activate irq remapping in PIIX */
124 pci_config_writeb(pci->bdf, 0x60 + i, irq);
126 outb(elcr[0], 0x4d0);
127 outb(elcr[1], 0x4d1);
128 dprintf(1, "PIIX3/PIIX4 init: elcr=%02x %02x\n", elcr[0], elcr[1]);
131 static const struct pci_device_id pci_isa_bridge_tbl[] = {
132 /* PIIX3/PIIX4 PCI to ISA bridge */
133 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0,
134 piix_isa_bridge_init),
135 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_0,
136 piix_isa_bridge_init),
141 static void storage_ide_init(struct pci_device *pci, void *arg)
143 /* IDE: we map it as in ISA mode */
144 pci_set_io_region_addr(pci, 0, PORT_ATA1_CMD_BASE);
145 pci_set_io_region_addr(pci, 1, PORT_ATA1_CTRL_BASE);
146 pci_set_io_region_addr(pci, 2, PORT_ATA2_CMD_BASE);
147 pci_set_io_region_addr(pci, 3, PORT_ATA2_CTRL_BASE);
150 /* PIIX3/PIIX4 IDE */
151 static void piix_ide_init(struct pci_device *pci, void *arg)
154 pci_config_writew(bdf, 0x40, 0x8000); // enable IDE0
155 pci_config_writew(bdf, 0x42, 0x8000); // enable IDE1
158 static void pic_ibm_init(struct pci_device *pci, void *arg)
160 /* PIC, IBM, MPIC & MPIC2 */
161 pci_set_io_region_addr(pci, 0, 0x80800000 + 0x00040000);
164 static void apple_macio_init(struct pci_device *pci, void *arg)
167 pci_set_io_region_addr(pci, 0, 0x80800000);
170 static const struct pci_device_id pci_class_tbl[] = {
172 PCI_DEVICE_CLASS(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_1,
173 PCI_CLASS_STORAGE_IDE, piix_ide_init),
174 PCI_DEVICE_CLASS(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB,
175 PCI_CLASS_STORAGE_IDE, piix_ide_init),
176 PCI_DEVICE_CLASS(PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE,
179 /* PIC, IBM, MIPC & MPIC2 */
180 PCI_DEVICE_CLASS(PCI_VENDOR_ID_IBM, 0x0046, PCI_CLASS_SYSTEM_PIC,
182 PCI_DEVICE_CLASS(PCI_VENDOR_ID_IBM, 0xFFFF, PCI_CLASS_SYSTEM_PIC,
186 PCI_DEVICE_CLASS(PCI_VENDOR_ID_APPLE, 0x0017, 0xff00, apple_macio_init),
187 PCI_DEVICE_CLASS(PCI_VENDOR_ID_APPLE, 0x0022, 0xff00, apple_macio_init),
192 /* PIIX4 Power Management device (for ACPI) */
193 static void piix4_pm_init(struct pci_device *pci, void *arg)
196 // acpi sci is hardwired to 9
197 pci_config_writeb(bdf, PCI_INTERRUPT_LINE, 9);
199 pci_config_writel(bdf, 0x40, PORT_ACPI_PM_BASE | 1);
200 pci_config_writeb(bdf, 0x80, 0x01); /* enable PM io space */
201 pci_config_writel(bdf, 0x90, PORT_SMB_BASE | 1);
202 pci_config_writeb(bdf, 0xd2, 0x09); /* enable SMBus io space */
205 static const struct pci_device_id pci_device_tbl[] = {
206 /* PIIX4 Power Management device (for ACPI) */
207 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3,
213 static void pci_bios_init_device(struct pci_device *pci)
216 dprintf(1, "PCI: init bdf=%02x:%02x.%x id=%04x:%04x\n"
217 , pci_bdf_to_bus(bdf), pci_bdf_to_dev(bdf), pci_bdf_to_fn(bdf)
218 , pci->vendor, pci->device);
220 pci_init_device(pci_class_tbl, pci, NULL);
222 /* enable memory mappings */
223 pci_config_maskw(bdf, PCI_COMMAND, 0, PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
225 /* map the interrupt */
226 int pin = pci_config_readb(bdf, PCI_INTERRUPT_PIN);
228 pci_config_writeb(bdf, PCI_INTERRUPT_LINE, pci_slot_get_irq(bdf, pin));
230 pci_init_device(pci_device_tbl, pci, NULL);
233 static void pci_bios_init_devices(void)
235 struct pci_device *pci;
237 if (pci_bdf_to_bus(pci->bdf) != 0)
238 // Only init devices on host bus.
240 pci_bios_init_device(pci);
244 pci_init_device(pci_isa_bridge_tbl, pci, NULL);
249 /****************************************************************
251 ****************************************************************/
254 pci_bios_init_bus_rec(int bus, u8 *pci_bus)
259 dprintf(1, "PCI: %s bus = 0x%x\n", __func__, bus);
261 /* prevent accidental access to unintended devices */
262 foreachbdf(bdf, bus) {
263 class = pci_config_readw(bdf, PCI_CLASS_DEVICE);
264 if (class == PCI_CLASS_BRIDGE_PCI) {
265 pci_config_writeb(bdf, PCI_SECONDARY_BUS, 255);
266 pci_config_writeb(bdf, PCI_SUBORDINATE_BUS, 0);
270 foreachbdf(bdf, bus) {
271 class = pci_config_readw(bdf, PCI_CLASS_DEVICE);
272 if (class != PCI_CLASS_BRIDGE_PCI) {
275 dprintf(1, "PCI: %s bdf = 0x%x\n", __func__, bdf);
277 u8 pribus = pci_config_readb(bdf, PCI_PRIMARY_BUS);
279 dprintf(1, "PCI: primary bus = 0x%x -> 0x%x\n", pribus, bus);
280 pci_config_writeb(bdf, PCI_PRIMARY_BUS, bus);
282 dprintf(1, "PCI: primary bus = 0x%x\n", pribus);
285 u8 secbus = pci_config_readb(bdf, PCI_SECONDARY_BUS);
287 if (*pci_bus != secbus) {
288 dprintf(1, "PCI: secondary bus = 0x%x -> 0x%x\n",
291 pci_config_writeb(bdf, PCI_SECONDARY_BUS, secbus);
293 dprintf(1, "PCI: secondary bus = 0x%x\n", secbus);
296 /* set to max for access to all subordinate buses.
297 later set it to accurate value */
298 u8 subbus = pci_config_readb(bdf, PCI_SUBORDINATE_BUS);
299 pci_config_writeb(bdf, PCI_SUBORDINATE_BUS, 255);
301 pci_bios_init_bus_rec(secbus, pci_bus);
303 if (subbus != *pci_bus) {
304 dprintf(1, "PCI: subordinate bus = 0x%x -> 0x%x\n",
308 dprintf(1, "PCI: subordinate bus = 0x%x\n", subbus);
310 pci_config_writeb(bdf, PCI_SUBORDINATE_BUS, subbus);
315 pci_bios_init_bus(void)
318 pci_bios_init_bus_rec(0 /* host bus */, &pci_bus);
322 /****************************************************************
324 ****************************************************************/
326 static u32 pci_size_roundup(u32 size)
328 int index = __fls(size-1)+1;
333 pci_bios_get_bar(struct pci_device *pci, int bar, u32 *val, u32 *size)
335 u32 ofs = pci_bar(pci, bar);
337 u32 old = pci_config_readl(bdf, ofs);
340 if (bar == PCI_ROM_SLOT) {
341 mask = PCI_ROM_ADDRESS_MASK;
342 pci_config_writel(bdf, ofs, mask);
344 if (old & PCI_BASE_ADDRESS_SPACE_IO)
345 mask = PCI_BASE_ADDRESS_IO_MASK;
347 mask = PCI_BASE_ADDRESS_MEM_MASK;
348 pci_config_writel(bdf, ofs, ~0);
350 *val = pci_config_readl(bdf, ofs);
351 pci_config_writel(bdf, ofs, old);
352 *size = (~(*val & mask)) + 1;
355 static void pci_bios_bus_reserve(struct pci_bus *bus, int type, u32 size)
359 index = pci_size_to_index(size, type);
360 size = pci_index_to_size(index, type);
361 bus->r[type].count[index]++;
362 bus->r[type].sum += size;
363 if (bus->r[type].max < size)
364 bus->r[type].max = size;
367 static void pci_bios_check_devices(struct pci_bus *busses)
369 dprintf(1, "PCI: check devices\n");
371 // Calculate resources needed for regular (non-bus) devices.
372 struct pci_device *pci;
374 if (pci->class == PCI_CLASS_BRIDGE_PCI) {
375 busses[pci->secondary_bus].bus_dev = pci;
378 struct pci_bus *bus = &busses[pci_bdf_to_bus(pci->bdf)];
380 for (i = 0; i < PCI_NUM_REGIONS; i++) {
382 pci_bios_get_bar(pci, i, &val, &size);
386 pci_bios_bus_reserve(bus, pci_addr_to_type(val), size);
387 pci->bars[i].addr = val;
388 pci->bars[i].size = size;
389 pci->bars[i].is64 = (!(val & PCI_BASE_ADDRESS_SPACE_IO) &&
390 (val & PCI_BASE_ADDRESS_MEM_TYPE_MASK)
391 == PCI_BASE_ADDRESS_MEM_TYPE_64);
393 if (pci->bars[i].is64)
398 // Propagate required bus resources to parent busses.
400 for (secondary_bus=MaxPCIBus; secondary_bus>0; secondary_bus--) {
401 struct pci_bus *s = &busses[secondary_bus];
404 struct pci_bus *parent = &busses[pci_bdf_to_bus(s->bus_dev->bdf)];
406 for (type = 0; type < PCI_REGION_TYPE_COUNT; type++) {
407 u32 limit = (type == PCI_REGION_TYPE_IO) ?
408 PCI_BRIDGE_IO_MIN : PCI_BRIDGE_MEM_MIN;
409 s->r[type].size = s->r[type].sum;
410 if (s->r[type].size < limit)
411 s->r[type].size = limit;
412 s->r[type].size = pci_size_roundup(s->r[type].size);
413 pci_bios_bus_reserve(parent, type, s->r[type].size);
415 dprintf(1, "PCI: secondary bus %d sizes: io %x, mem %x, prefmem %x\n",
417 s->r[PCI_REGION_TYPE_IO].size,
418 s->r[PCI_REGION_TYPE_MEM].size,
419 s->r[PCI_REGION_TYPE_PREFMEM].size);
423 #define ROOT_BASE(top, sum, max) ALIGN_DOWN((top)-(sum),(max) ?: 1)
425 // Setup region bases (given the regions' size and alignment)
426 static int pci_bios_init_root_regions(struct pci_bus *bus, u32 start, u32 end)
428 bus->r[PCI_REGION_TYPE_IO].base = 0xc000;
430 int reg1 = PCI_REGION_TYPE_PREFMEM, reg2 = PCI_REGION_TYPE_MEM;
431 if (bus->r[reg1].sum < bus->r[reg2].sum) {
432 // Swap regions so larger area is more likely to align well.
433 reg1 = PCI_REGION_TYPE_MEM;
434 reg2 = PCI_REGION_TYPE_PREFMEM;
436 bus->r[reg2].base = ROOT_BASE(end, bus->r[reg2].sum, bus->r[reg2].max);
437 bus->r[reg1].base = ROOT_BASE(bus->r[reg2].base, bus->r[reg1].sum
439 if (bus->r[reg1].base < start)
440 // Memory range requested is larger than available.
446 /****************************************************************
448 ****************************************************************/
450 static void pci_bios_init_bus_bases(struct pci_bus *bus)
452 u32 base, newbase, size;
455 for (type = 0; type < PCI_REGION_TYPE_COUNT; type++) {
456 dprintf(1, " type %s max %x sum %x base %x\n", region_type_name[type],
457 bus->r[type].max, bus->r[type].sum, bus->r[type].base);
458 base = bus->r[type].base;
459 for (i = ARRAY_SIZE(bus->r[type].count)-1; i >= 0; i--) {
460 size = pci_index_to_size(i, type);
461 if (!bus->r[type].count[i])
463 newbase = base + size * bus->r[type].count[i];
464 dprintf(1, " size %8x: %d bar(s), %8x -> %8x\n",
465 size, bus->r[type].count[i], base, newbase - 1);
466 bus->r[type].bases[i] = base;
472 static u32 pci_bios_bus_get_addr(struct pci_bus *bus, int type, u32 size)
476 index = pci_size_to_index(size, type);
477 addr = bus->r[type].bases[index];
478 bus->r[type].bases[index] += pci_index_to_size(index, type);
482 #define PCI_IO_SHIFT 8
483 #define PCI_MEMORY_SHIFT 16
484 #define PCI_PREF_MEMORY_SHIFT 16
486 static void pci_bios_map_devices(struct pci_bus *busses)
488 // Setup bases for root bus.
489 dprintf(1, "PCI: init bases bus 0 (primary)\n");
490 pci_bios_init_bus_bases(&busses[0]);
492 // Map regions on each secondary bus.
494 for (secondary_bus=1; secondary_bus<=MaxPCIBus; secondary_bus++) {
495 struct pci_bus *s = &busses[secondary_bus];
498 u16 bdf = s->bus_dev->bdf;
499 struct pci_bus *parent = &busses[pci_bdf_to_bus(bdf)];
501 for (type = 0; type < PCI_REGION_TYPE_COUNT; type++) {
502 s->r[type].base = pci_bios_bus_get_addr(
503 parent, type, s->r[type].size);
505 dprintf(1, "PCI: init bases bus %d (secondary)\n", secondary_bus);
506 pci_bios_init_bus_bases(s);
508 u32 base = s->r[PCI_REGION_TYPE_IO].base;
509 u32 limit = base + s->r[PCI_REGION_TYPE_IO].size - 1;
510 pci_config_writeb(bdf, PCI_IO_BASE, base >> PCI_IO_SHIFT);
511 pci_config_writew(bdf, PCI_IO_BASE_UPPER16, 0);
512 pci_config_writeb(bdf, PCI_IO_LIMIT, limit >> PCI_IO_SHIFT);
513 pci_config_writew(bdf, PCI_IO_LIMIT_UPPER16, 0);
515 base = s->r[PCI_REGION_TYPE_MEM].base;
516 limit = base + s->r[PCI_REGION_TYPE_MEM].size - 1;
517 pci_config_writew(bdf, PCI_MEMORY_BASE, base >> PCI_MEMORY_SHIFT);
518 pci_config_writew(bdf, PCI_MEMORY_LIMIT, limit >> PCI_MEMORY_SHIFT);
520 base = s->r[PCI_REGION_TYPE_PREFMEM].base;
521 limit = base + s->r[PCI_REGION_TYPE_PREFMEM].size - 1;
522 pci_config_writew(bdf, PCI_PREF_MEMORY_BASE, base >> PCI_PREF_MEMORY_SHIFT);
523 pci_config_writew(bdf, PCI_PREF_MEMORY_LIMIT, limit >> PCI_PREF_MEMORY_SHIFT);
524 pci_config_writel(bdf, PCI_PREF_BASE_UPPER32, 0);
525 pci_config_writel(bdf, PCI_PREF_LIMIT_UPPER32, 0);
528 // Map regions on each device.
529 struct pci_device *pci;
531 if (pci->class == PCI_CLASS_BRIDGE_PCI)
534 dprintf(1, "PCI: map device bdf=%02x:%02x.%x\n"
535 , pci_bdf_to_bus(bdf), pci_bdf_to_dev(bdf), pci_bdf_to_fn(bdf));
536 struct pci_bus *bus = &busses[pci_bdf_to_bus(bdf)];
538 for (i = 0; i < PCI_NUM_REGIONS; i++) {
539 if (pci->bars[i].addr == 0)
542 int type = pci_addr_to_type(pci->bars[i].addr);
543 u32 addr = pci_bios_bus_get_addr(bus, type, pci->bars[i].size);
544 dprintf(1, " bar %d, addr %x, size %x [%s]\n",
545 i, addr, pci->bars[i].size, region_type_name[type]);
546 pci_set_io_region_addr(pci, i, addr);
548 if (pci->bars[i].is64) {
550 pci_set_io_region_addr(pci, i, 0);
557 /****************************************************************
559 ****************************************************************/
564 if (CONFIG_COREBOOT || usingXen()) {
565 // PCI setup already done by coreboot or Xen - just do probe.
570 dprintf(3, "pci setup\n");
572 u32 start = BUILD_PCIMEM_START;
573 u32 end = BUILD_PCIMEM_END;
575 dprintf(1, "=== PCI bus & bridge init ===\n");
576 if (pci_probe_host() != 0) {
581 dprintf(1, "=== PCI device probing ===\n");
584 dprintf(1, "=== PCI new allocation pass #1 ===\n");
585 struct pci_bus *busses = malloc_tmp(sizeof(*busses) * (MaxPCIBus + 1));
590 memset(busses, 0, sizeof(*busses) * (MaxPCIBus + 1));
591 pci_bios_check_devices(busses);
592 if (pci_bios_init_root_regions(&busses[0], start, end) != 0) {
593 panic("PCI: out of address space\n");
596 dprintf(1, "=== PCI new allocation pass #2 ===\n");
597 pci_bios_map_devices(busses);
599 pci_bios_init_devices();